Overview of Server Chipsets

This chapter is from the book 

Other Third-Party Server Chipsets for Intel Processors

Although Intel and ServerWorks are the major producers of server-class chipsets for Intel server processors, they are not the only producers of these chipsets.

Other vendors, including VIA Technologies, IBM, and Hewlett-Packard have also produced server-class chipsets for Intel processors from the Pentium Pro and Pentium II through the Itanium 2. The following sections discuss the offerings from these companies.

VIA Technologies Chipsets for Intel Server Processors

Although VIA Technologies built a variety of chipsets for the P6 family of processors, only the following have been used in one-way and two-way servers:

• Apollo Pro 133A with VIA 694MP North Bridge (two-way servers) with VIA VT82694X (one-way servers)
• Apollo Pro 266/266T

Table 3.19 provides an overview of these chipsets.

Table 3.19. VIA Server-Class Chipset for P6 Processors

Feature	Apollo Pro 133A	Apollo Pro 266/266T
Part number	VT82694X or VT82C694MP	VT8633
Bus speed	66, 100, 133MHz	66, 100, 133MHz
Supported processors	Pentium II, III	Pentium III (Tualatin)
Form factor	Slot 1, Socket 370	Socket 370
SMP (dual CPUs)	Yes (with VT82C694MP NB only)	Yes
Memory types	PC66, 100, 133 SDRAM, EDO	PC100, 133 SDRAM, DDR200, 266
Parity/ECC	Yes	No
Maximum memory	4GB	4GB
PCI support	2.2	2.2
PCI speed/ width	33MHz/32-bit	33MHz/32-bit
AGP slot	2x, 4x	2x, 4x
Integrated video	No	No
South Bridge	VT82C596B or VT82C686A	VT8233C [1]

Although some of VIA Technologies Pentium 4–class chipsets are also compatible with the Xeon, litigation has discouraged motherboard makers from adopting them for server-class motherboards.

The VIA Technologies Apollo Pro 133A Chipset

The VIA Apollo Pro133A chipset was a North Bridge/South Bridge chipset designed to support Slot 1 and Socket 370 processors such as the Intel Pentium III, Intel Celeron, and VIA Cyrix III. The Apollo Pro133A is based on the previous Pro133, with additional features added. Note that there are actually two versions of this chipset. The original version was released in fall 1999 and supported single-processor installations and used the VIA 694 North Bridge. In spring 2000, VIA Technologies developed a dual-processor–compatible version using the 694MP North Bridge.

Features of the Apollo Pro133A include the following:

• AGP 4x graphics bus support
• 133/100/66MHz processor bus support
• PC-133 SDRAM memory interface
• UltraATA/66 interface
• Support for four USB 1.1 ports
• AC '97 link for audio and modem
• Hardware monitoring
• Power management

The VIA Apollo Pro133A chipset was a two-chip set consisting of the VT82C694X North Bridge controller (single-CPU version) or VT82C694MP North Bridge controller (dual-CPU version) and a choice of a VT82C596B or VT82C686A South Bridge controller.

Table 3.20 provides an overview of the features of the South Bridge chips used in the Apollo Pro 133A chipset.

Table 3.20. VIA South Bridge Chips Used with Apollo Pro 133A

South Bridge Chip	Number of USB 1.1 Ports	ATA Support	Integrated Sound	Integrated Super I/O
VT82C586A	—	ATA-33	No	No
VT82C596B	4	ATA-66	AC '97	Yes

A number of vendors produced dual-processor server motherboards using the Apollo Pro 133A chipset.

The VIA Technologies Apollo Pro266 Chipset

The VIA Apollo Pro266 is a high-performance North Bridge/South Bridge chipset designed to support Socket 370 processors, including the Pentium III. The Apollo Pro266 was the first chipset from VIA to replace the traditional PCI (133MBps) connection between North Bridge and South Bridge chips with VIA's 4x V-Link interconnect, which runs at 266MBps. The Apollo Pro 266 was introduced in late 2000.

Features of the Apollo Pro266 include the following:

• AGP 2x/4x graphics bus support
• 133/100/66MHz processor bus support
• PC-100/133 SDRAM and PC200/266 DDR SDRAM memory interface
• ATA-100 IDE interface
• Support for six USB 1.1 ports
• Integrated AC '97 six-channel audio
• Integrated MC '97 modem
• Integrated 10/100BASE-T Ethernet and 1/10MHz Home PNA networking
• Hardware monitoring
• ACPI/On Now! power management
• VIA 4x (266MBps) V-Link North Bridge/South Bridge interconnect

The VIA Apollo Pro266 chipset was a two-chip set consisting of the 552-pin BGA VT8633 North Bridge controller and the 376-pin BGA VT8233 South Bridge controller. The Apollo Pro266T is an updated version of this chipset that supports Pentium III Tualatin processors. Figure 3.27 shows the architecture of the Apollo Pro266 chipset.

Because of the V-Link high-speed interconnect between the North Bridge and South Bridge, PCI is managed by the South Bridge. This is similar to the way in which Intel Hub Architecture works, and this basic architecture has been followed by all subsequent VIA chipsets that use V-Link architecture.

The Apollo Pro 266 and 266T (Tualatin-compatible version) chipsets have been used by a variety of vendors to produce both standard ATX form factor and various types of single-board–computer servers using one or two processors.

IBM Chipsets for Intel Server-Class Processors

IBM has produced several chipsets for its own lines of Intel server-class processors:

• XA-32 (Summit)— Supports 32-bit Xeon processors.
• XA-32 second-generation— Supports 32-bit Xeon processors.
• XA-64— Supports Itanium 2 processors.
• XA-64e (Hurricane)— Supports 64-bit Xeon processors. The following sections provide details of these chipsets.

The XA-32 Chipset for Xeon MP/DP

IBM's XA-32 chipset, codenamed Summit, was first fully implemented in the IBM @server xSeries 440, released in September 2002. This chipset, developed by the IBM Microelectronics Division in Austin, Texas, has the following major features:

• Support for Xeon MP Foster processors for two-way, four-way, or eight-way implementations
• Support for Xeon DP Prestonia processors for two-way or four-way implementations (the XA-32 chipset permits four-way operation with Xeon DP processors, although Intel designed the Xeon DP for single- or two-way operation only)
• Support for memory mirroring, chipkill, and Memory ProteXion features for memory reliability
• Support for 64-bit PCI-X slots at 133MHz, 100MHz, and 66MHz speeds

The components of the XA-32 chipset include the following:

• The Cyclone memory controller— Each four-way installation requires a memory controller. The memory controller is located in the SMP expansion module.
• The Twister processor and cache controller— Each eight-way installation requires a cache controller. The processor and cache controller is located in the SMP expansion module.
• Two Winnipeg PCI bridges— The PCI bridges are connected to the Cyclone memory controller. Typically, one PCI bridge is used for interfacing to 133MHz and 100MHz PCI-X slots, and the other PCI bridge is used for interfacing to 66MHz PCI-X slots, video, USB, keyboard/mouse, SCSI, Gigabit Ethernet, and other I/O devices, as well as the Remote Expansion I/O (RXE) port. The RXE port connects to the optional RXE-100 enclosure, which supports 12 PCI-X slots.

Figures 3.28 and 3.29 show the major components of the XA-32 chipset in a 4-way (top) and 8-way (bottom) configuration, respectively. Each 8-way configuration is called a node, and two nodes can be connected via the SMP expansion ports to create a 16-way processor complex.

The XA-32 Second-Generation Chipset for Xeon MP/DP

The second generation of the IBM XA-32 chipset is used in IBM xSeries servers such as the x365, x445, and x455. It has the following major differences from the original XA-32:

• Improved Cyclone memory controller (version 3.0) for lower memory latency than in the original XA-32 chipset.
• Improved Winnipeg PCI bridges (version 4.0) that support 133MHz PCI-X expansion slots.
• Support for Gallatin versions of the Xeon MP processor. Gallatin versions of the Xeon MP run at speeds up to 3GHz.

	See "Xeon Processors," p. 114.

The block diagram shown in Figure 3.28 applies to both original and second-generation XA-32–based systems.

The XA-64 Chipset for Itanium 2

The IBM XA-64 chipset, codenamed Summit, was first used in the xSeries 450 server released in mid-2003. It was developed by the IBM Microelectronics Division. It has the following major features:

• Support for one to four Itanium 2 Madison processors
• Support for memory mirroring, chipkill, and Memory ProteXion features for memory reliability
• Support for 64-bit PCI-X slots at 133MHz, 100MHz, and 66MHz speeds

The components of the XA-64 chipset include the following:

• The Cyclone memory controller— The memory controller is located in the memory-board assembly.
• The Tornado processor and cache controller— The processor and cache controller is located in the processor board assembly. It connects to the processors as well as to 64MB of L4 cache, a feature IBM calls XceL4 Server Accelerator Cache.
• Two Winnipeg PCI bridges— The PCI bridges are connected to the Cyclone memory controller. Typically, one PCI bridge is used for interfacing to 133MHz and 100MHz PCI-X slots, and the other PCI bridge is used for interfacing to 66MHz PCI-X slots, video, USB, keyboard/mouse, SCSI, Gigabit Ethernet, and other I/O devices, as well as the RXE port. The RXE port connects to the optional RXE-100 enclosure, which supports 12 PCI-X slots.

Figure 3.30 shows the major components of the XA-64 chipset in a four-way configuration.

The XA-64e Chipset for 64-Bit Xeon Processors

IBM's XA-64e chipset, codenamed Hurricane, is used in Xeon EM64T-compatible IBM @servers such as the xSeries 366. This chipset, developed by the IBM Microelectronics Division in Austin, Texas, has the following major features:

• Support for one to four Xeon MP Cranford processors supporting EM64T (Intel's term for 64-bit extensions to IA-32 architecture)
• Support for memory mirroring (works with hot-swapping), chipkill, and Memory ProteXion features for memory reliability
• Support for memory hot-swapping or hot-adding (hot-adding requires that memory mirroring be disabled)
• Support for 64-bit PCI-X 2.0 Active PCI slots running at 266MHz.

	See "Xeon MP with EM64T Support," p. 120.

The components of the XA-64e chipset include the following:

• The Hurricane memory and I/O controller— The memory controller provides a one-chip interface between the processor(s), memory, and the Winnipeg PCI-X bridge chips. Memory is plugged in to SMI2 memory cards (see Figure 3.31).
  

  Figure 3.31 A typical four-way configuration using the IBM XA-64e chipset.

• Two Calgary PCI-X 2.0 bridges— The PCI bridge chips are connected to the Hurricane memory and I/O controller. Typically, one PCI bridge is used to interface to four of the PCI-X 2.0 slots, and the other PCI bridge is used for interfacing to two PCI-X 2.0 slots, video, USB 2.0 ports, RAID, Gigabit Ethernet, and South Bridge chips. PCI-X 2.0 slots run at speeds up to 266MHz.

Figure 3.31 shows the major components of the XA-64e chipset in a four-way configuration.

Hewlett-Packard Server Chipsets for Intel Processors

In addition to using server chipsets from third-party vendors, Hewlett-Packard has developed two distinct lines of chipsets for its servers:

• The F8 (an improved version of the Corollary/Compaq Profusion chipset) supports Xeon MP processors.
• The zx1 is the first of a line of chipsets that support PA-RISC or Itanium-family–equipped Hewlett-Packard servers in the Superdome (originally Half Dome) family.

The following sections discuss the major features of these chipsets.

The F8 Chipset for Xeon MP

The Hewlett-Packard F8 chipset was developed by Compaq as a follow-on to the eight-way Corollary chipset co-developed by Corollary and Compaq. Hewlett-Packard obtained the F8 chipset as part of its merger with Compaq. The F8 chipset is used in the Hewlett-Packard ProLinea DL740 and DL760-series eight-way servers.

The F8 chipset's major features include the following:

• Support for eight Xeon MP processors
• Dual-channel memory supporting PC133 SDRAM
• Support for PCI and PCI-X expansion slots
• Hot-plug RAID memory
• Up to 64GB of addressable memory

The F8 chipset has the following major components:

• Five F8 dual memory controllers— Four are used for data and one is used to store parity information. Each is connected to a memory cartridge containing up to eight DIMMs of dual-channel PC133 SDRAM using cache-line interleaving for better performance. Memory can be hot-plugged (in or out) without shutting down the server, and the memory controllers can correct single-bit and double-bit memory errors as well as correct DIMM failures.
• One F8 crossbar switch— The crossbar switch handles traffic running at 400 megatransfers per second between the memory controllers, processors, and the PCI bridges. It uses multiple buffers and 128 cache lines to manage eight-way traffic.
• One F8 cache coherence filter— A cache coherence filter connected to the crossbar switch prevents unnecessary traffic between L2 caches in different processors.
• Up to four PCI-X bridges with PCI hot-plug controllers— Each bridge supports two 64-bit PCI-X bus segments, and each segment can be configure to run in 33/66MHz PCI mode or 66/100MHz PCI-X mode.

Figure 3.32 illustrates the major components of the F8 chipset.

The zx1 Chipset for Itanium 2 McKinley

The Hewlett-Packard zx1 Pluto chipset for the Itanium 2 processor uses only two or three chips, making it the simplest chipset available for the Itanium 2 processor. However, although the zx1 is designed to work in one-way and two-way workstation configurations as well as in two-way and four-way server applications, it does not support eight-way implementations.

The Hewlett-Packard zx1 chipset has the following components in two-way configurations:

• Hewlett-Packard chipset and memory I/O controller— This chip connects memory and processors to each other. This is designed for DDR SDRAM memory, unlike the E8870, which uses translator hubs.
• Hewlett-Packard chipset I/O adapter— This chip can be used as a bridge to an AGP 4x slot for workstation uses, PCI-X slots up to 133MHz, and for various types of I/O, including ATA/IDE, USB, SCSI, and networking.

When used in a four-way server implementation, two Hewlett-Packard zx1 scalable memory adapter chips are added to the chipset to connect the greater number of memory banks supported, and additional Hewlett-Packard Chipset I/O adapters are used to support additional 66MHz PCI-X devices. Some of Hewlett-Packard's latest servers based on the zx1 incorporate two Itanium 2 processors in the mx2 dual processor module, enabling the chipset to support eight-way implementations.

Figure 3.33 illustrates a typical two-way (workstation/server) implementation of the zx1 chipset, and Figure 3.34 shows a typical four-way server implementation.

The sx1000 Pinnacles Chipset

The Hewlett-Packard Super-Scalable Processor chipset sx1000, codenamed Pinnacles, supports eight-way or higher implementations. Like the zx1, it can use single- or dual-processor cartridges. However, compared to other Itanium 2 chipsets, it has several distinct features:

• The sx1000 uses a cell architecture: Each cell comprises a cell controller chip and eight memory buffer chips. Each cell can contain four CPU modules and up to 32 PC133 registered SDRAM modules. The cell controller chip connects directly to the PCI-X system bus adapter, which connects to PCI-X bridge chips. See Figure 3.35.
  

  Figure 3.35 The block diagram of a cell board from a Hewlett-Packard sx1000 Pinnacles chipset (Hewlett-Packard)sx1000 chipset.

• sx1000-based servers include 2, 4, 8, or 16 cells. (Each cell includes four or eight processors, depending on whether single- or dual-processor cartridges are used; see Figure 3.36.)
  

  Figure 3.36 The block diagram of an mx2 processor cartridge.

• When four or more cells are connected together, one or more crossbar switches are used. One crossbar switch is used for each group of four cells (16 processor sockets). For example, in a 64-socket system, four crossbar switches would be used.

Figure 3.35 illustrates the block diagram of a four-way or eight-way sx1000 cell board. A four-way cell board uses four standard Itanium 2 processors, while an eight-way cell board uses four Hewlett-Packard mx2 processor cartridges, each of which contains two Itanium 2 processors along with 32MB L4 memory cache.

Figure 3.36 illustrates the block diagram of an mx2 processor cartridge.

The sx1000 is designed to be highly scalable to handle server tasks of virtually any size and complexity.