A+ Certification Preparation: System Resources

This chapter is from the book

A+ Certification Training Guide (Exams 220-221, 220-222), 4th Edition

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This chapter is from the book

This chapter is from the book 

A+ Certification Training Guide (Exams 220-221, 220-222), 4th Edition

Learn More Buy

Extended I/O

In addition to the millions of possible memory locations in a PC, typically thousands of addresses are set aside for input and output devices in a system. In order for any device to operate with the system's microprocessor, it must have an address (or group of addresses) where the system can find it.

When discussing the standard I/O ports for PCs, it is common to differentiate between traditional standard ports that include

• Keyboard port

• Centronic parallel ports

• RS-232C serial ports

• Game ports

And newer standard ports that include

• PS/2 mouse and keyboard ports

• USB ports

• IEEE-1394 Firewire ports

• Infrared ports

• Improved parallel ports

Moving Data

The most frequent operation performed in a computer is the movement of information from one location to another. This information is moved in the form of words. Basically, there are two modes in which the words can be transferred. These modes are parallel mode—where an entire word is transferred from location A to location B by a set of parallel conductors at one instant—and serial mode—where the bits of the word are transmitted along a single conductor, one bit at a time.

Serial transfers require more time to accomplish than parallel transfers because a clock cycle must be used for each bit transferred. A parallel transfer requires only one clock pulse. Examples of both parallel and serial transfers are depicted in Figure 3.1.

Figure 3.1 Parallel and serial data transfers.

Initiating I/O Transfers

During normal program execution, the microprocessor constantly reads from or writes to memory locations. The program can also call on the microprocessor to read from or write to one of the system's I/O devices. Regardless of how the peripheral is connected to the system (serial or parallel), one of four methods can be used to initiate data transfer between the system and the peripheral. These four methods are listed as follows:

• Polling—The microprocessor examines the status of the peripheral under program control.

• Programmed I/O—The microprocessor alerts the designated peripheral by applying its address to the system's address bus.

• Interrupt-driven I/O—The peripheral alerts the microprocessor that it's ready to transfer data.

• Direct Memory Access (DMA)—The intelligent peripheral assumes control of the system's buses to conduct direct transfers with primary memory.

Polling and Programmed I/O

Both polling and programmed I/O represent software approaches to data transfer; interrupt-driven and DMA transfers, on the other hand, are basically hardware approaches. Using the polling method, the software periodically checks with the system's I/O devices to determine whether any device is ready to conduct a data transfer. The programmed I/O method calls for the microprocessor to alert the desired peripheral of an I/O operation by issuing its address to the address bus. The peripheral can delay the transfer by asserting its busy line.

Interrupts

In the course of normal operations, the various I/O devices attached to a PC, such as the keyboard and disk drives, require servicing from the system's microprocessor. Because these service requests can happen at any time and tend to require immediate attention, I/O devices generally have the capability to interrupt the microprocessor while it is executing a program. The I/O device accomplishes this by issuing a Maskable Interrupt (IRQ) input signal to the microprocessor. Each device in a PC-compatible system that is capable of interrupting the microprocessor must be assigned its own, unique IRQ number. The system uses this number to identify which device is in need of service.

Two varieties of interrupts are used in microcomputers:

• Maskable Interrupts (IRQs)—Interrupts that the system microprocessor can ignore under certain conditions.

• Non-Maskable Interrupts (NMI)—Very serious interrupts to which the system microprocessor must always respond. NMI conditions normally result in the system being shut down.

The device that requires service contacts the system's interrupt controller, which in turn contacts the system microprocessor and supplies it with information about where to service the device that issued the request. The processor stops what it is doing, stores the information that it is working with, jumps to the program servicing that interrupt, runs the service routine, and then returns to its original operation. A programmable interrupt controller, and its relationship to the system's microprocessor, is illustrated in Figure 3.2.

Figure 3.2 A programmable interrupt controller operation.

Of the 16 interrupt channels (IRQ0 through IRQ15) available, three are generally used inside the system board's chipset. Therefore, they do not have external IRQ pins. The other 13 IRQ inputs are available to the system for user-definable interrupt functions. Each IRQ input is assigned a priority level. IRQ0 is the highest, and IRQ15 is the lowest. The internally connected channels are

Table 3.1 shows the designations for the various interrupt levels in the system.

Table 3.1 System Interrupt Levels

There are two serious system board-based conditions that will cause a Non-Maskable Interrupt (NMI) signal to be sent to the microprocessor. The first condition occurs when an active IO Channel Check (IOCHCK) signal is received from an adapter card located in one of the board's expansion slots. The other event that will cause an NMI signal to be generated is the occurrence of a Parity Check (PCK) error in the system's DRAM memory. Because these errors indicate that information from I/O devices or memory cannot be trusted, the NMI signal will cause the system to shut down without storing any of the potentially bad data.

Reference Shelf For more information, refer to the Electronic Reference Shelf, "How Interrupts Work," located on the CD that accompanies this book.

Direct Memory Access

Direct Memory Access operations are very similar to interrupt-driven I/O operations, except that the controller does not ask the system microprocessor to stop what it is doing to manage the I/O operation. Instead, the DMA controller asks the microprocessor to get out of the way so that it can control the system and handle the I/O transfer. The DMA controller is a specialized microprocessor that can conduct the transfer much faster than the standard microprocessor can. Table 3.2 describes the system's DMA channel designations.

Table 3.2 System's DMA Channel Designations

The system's FDD controller uses DMA channel 2 by default. Newer parallel port modes, such as ECP mode, can be assigned to any of the other open DMA channels. DMA channel 4 is used internally to cascade the two, four-channel DMA controllers together.

Onboard I/O

When dealing with a PC-compatible, there are two forms of I/O to contend with. These include the system board's onboard I/O as well as peripheral devices that interact with the system through its expansion slots.

Most of the I/O functions associated with PC-compatible systems have become so standardized that IC manufacturers produce them in single-chip ASIC formats. Figure 3.3 illustrates an ASIC for standard, AT-compatible system board functions.

Reference Shelf For more information, refer to the Electronic Reference Shelf, "How DMA Works," located on the CD that accompanies this book.

Figure 3.3 Onboard I/O.

Certain I/O connections have become standards associated with PC-compatibles. These include the system's parallel printer ports, RS-232 serial ports, and the game port. Figure 3.4 depicts an M/IO ASIC for standard peripheral control.

Figure 3.4 System I/O methods.

In both cases, the I/O controllers integrated into the ASIC are responsible for matching signal levels and protocols between the computer system and the I/O device. The system communicates with its onboard intelligent devices using I/O addresses. The onboard address decoder converts addresses from the address bus into enabling bits for the system's intelligent devices. These addresses are included in the overall I/O addressing map of the system.

In a PC-compatible system, standard I/O adapters employ the various I/O port addresses listed in Table 3.3. Notice that these addresses are redundant with those stated for the system's interrupt vectors given in Table 3.4. PC-compatible computers handle addresses differently depending on whether they are identified in software as memory or I/O addresses.

Table 3.3 I/O Port Addresses

Table 3.4 System Memory Map

Modems

As mentioned in Chapter 1, "Basic Terms and Concepts," modems come in two common types—internal and external. Both types of modems depend on a serial communication device called a Universal Asynchronous Receiver-Transmitter (UART) to carry out the serial-to-parallel and parallel-to-serial data conversions. In the case of an internal modem, the UART is normally located on the adapter card. With an external modem, the UART is usually provided by one of the PC's serial communications (COM) ports. The modem connects to the serial port through a standard RS-232 25-pin D-shell connector.

In the case of the internal modem, the UART in the modem normally replaces one of the two COM port UARTs provided by a typical PC system. If the COM port UART is not disabled, the system might have trouble differentiating between the two ports and a conflict can develop. Therefore, it is common practice to disable an onboard UART when an internal modem is installed. The COM ports can be enabled or disabled through the system's CMOS Setup—Peripherals screen.

In AT-style PCs, the first UART is normally used with the system's serial mouse. From the tables in this chapter, you can see that it resides at addresses 3F8 through 3FFh, uses IRQ4, and is assigned the designation of COM1. Therefore, the modem (or its host COM port) should be configured for addresses 278 through 27Fh, IRQ3, and COM2.

In ATX systems, the mouse has been provided with a special PS/2 mouse port, along with its own resources—including IRQ12. Therefore, a modem would be free to use COM1 or COM2 in these systems.

Floppy Drive Controllers

Most Pentium system boards contain the Floppy Disk drive Controller (FDC) circuitry and its physical interface connection. In older units, this circuitry and connector were typically located on an MI/O adapter card. The Pentium system board provides a standard 34-pin, two-row Berg connector as the FDD physical interface (typically labeled FD1). PC-compatible systems use a 34-pin flat ribbon cable as the FDD signal cable. This cable connects the system board's FDD interface with one or two floppy disk drives.

The FDC portion of the system board's chipset provides a programmable, logical interface for up to two FDD units. It resides in the I/O address range between locations 370 and 37Fh. The FDC receives and decodes instructions from the system to the floppy disk drive at these addresses. It also decodes these commands and generates the proper signals to carry out the command. Finally, it converts the data from the parallel format of the system to the encoded serial format used by the disk drive. The typical FDC divides the floppy disk into 80 tracks per side, with 9 or 18 512-byte sectors per side. This provides the system with 737,280 (720KB) or 1,474,560 (1.44MB) total bytes of storage on each diskette.

In a PC system, the FDC operates in conjunction with the system's DMA controller and is assigned to the DRQ-2 and DACK-2 lines. In operation, the FDC presents an active DRQ-2 signal to the DMA controller for every byte of data to be transferred. After the last byte has been transferred, the FDC interrupt is generated. The floppy disk drive controller is assigned the IRQ-6 channel in PC-compatible systems. The FDC generates an interrupt signal each time it receives a Read, Write, or Format command from the system.

Hard Drive Controllers

Typical Pentium-based system boards include one or two enhanced IDE controllers to handle the hard disk drive hosting function. Each controller can handle up to two IDE drives. This provides the PC with the capability of controlling up to four IDE devices. The first drive at each connector is called the master and the second is called the slave. The first, or Primary IDE, controller is assigned IRQ14, whereas the Secondary controller uses IRQ15 to interrupt the system. The system board supplies two 40-pin BERG connectors that are typically labeled IDE1 and IDE2. Each connector corresponds to an IDE controller.

Generally, the master drive doesn't have anything to do with the operation of the slave drive. Whether a drive operates as master or slave is typically determined by the settings of configuration jumpers on each drive. If the drive is the only unit attached to the host connector, it can be configured as a single drive. The address decoding logic on the host adapter will then oversee the selection of either drive. The first IDE drive controller responds to I/O addresses between 1F0h and 1F7h, whereas the second answers to addresses between 170h and 177h.

Older hard drives required that the CMOS Setup parameters of the computer match the parameters of the drive that was connected to the system, specifying such things as the number of R/W heads and number of cylinders being used. In those units, the drive needed to match one of the configurations in the computer's drive-parameter tables. This table was a function of the system's BIOS. However, the last entry in the table was typically reserved for user entered parameters that could be used for drives not listed in the table.

Most of the newer IDE drives include a feature called translation mode. These drives add a microprocessor to the controller's electronics that determines what configuration the computer expects, and then adjusts itself to mimic that drive layout, within the limitations of the drive's geometry. Because of the sector translation and matching work the IDE controller performs, the host system is isolated from the actual layout of the heads and cylinders on the drive. It only sees its logical configuration presented by the controller, which matches the CMOS setting. This makes the IDE interface a system-level interface.

A growing number of system boards include SCSI interface support in their BIOS. However, very few include a physical onboard interface connection. This interface is typically found on a SCSI host adapter card that plugs in to one of the system's expansion slots.

USB Ports

Most ATX system boards include dual Universal Serial Bus (USB) connectors as a standard part of their I/O port offering. The onboard USB controller resides between the I/O addresses of FF80 and FF9Fh. The USB controller is also assigned an IRQ channel (such as IRQ10) by the PnP process.

The operation of the port connections is controlled by settings in the system board's CMOS Setup Utility. In most cases, it will be necessary to access the CMOS Setup Utility's PCI Configuration screen to enable the USB function and assign the ports IRQ channels to use. If no USB device is being used with the system, the IRQ allocation should be set to NA to free up the IRQ line for use by other devices.

Infrared Port

Infrared Data Association (IrDA) ports are very popular with notebook computers. These ports provide short-distance wireless connections for different IrDA-compliant devices, such as printers and personal digital assistants. Because the IrDA port communicates by sending and receiving a serial stream of light pulses, it is normally configured to work with the UART of the system's second serial port. This arrangement must be established in the Peripherals page of the CMOS Setup utility, as illustrated in Figure 3.5. In this manner, the infrared port is assigned the same system resources normally reserved for the COM2/COM4 serial ports (that is, IRQ3, 2F8-2FFh, or 2E8-2Efh).

Figure 3.5 Enabling the infrared port.

To enable the IrDA port, the mode for the COM2 UART must be set to automatic and one of the infrared protocol settings (HPSIR or ASKIR) must be selected. In addition, the transmission duplex mode must be selected (normally half duplex). The operation of the infrared port and the second serial port are mutually exclusive. When the infrared option is enabled in CMOS, the second serial port will be disabled.