Register your product to gain access to bonus material or receive a coupon.
VLSI Design Methodology Development
- By Thomas Dillinger
- Published Jul 18, 2019 by Pearson.
Book
- Sorry, this book is no longer in print.
eBook
- Your Price: $96.89
- List Price: $113.99
- About Watermarked eBooks
This PDF will be accessible from your Account page after purchase and requires PDF reading software, such as Acrobat® Reader®.
The eBook requires no passwords or activation to read. We customize your eBook by discreetly watermarking it with your name, making it uniquely yours.
About
Features
- Reflect complexity, cost, resources, and schedules in planning a chip design project
- Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements
- Model functionality and behavior, validate designs, and verify formal equivalency
- Apply EDA tools for logic synthesis, placement, and routing
- Analyze timing, noise, power, and electrical issues
- Prepare for manufacturing release and bring-up, from mastering ECOs to qualification
Description
- Copyright 2020
- Dimensions: 7" x 9-1/8"
- Pages: 752
- Edition: 1st
- Book
- ISBN-10: 0-13-573241-7
- ISBN-13: 978-0-13-573241-0
- eBook
- ISBN-10: 0-13-573474-6
- ISBN-13: 978-0-13-573474-2
The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis
As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.
Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer’s perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels.
- Reflect complexity, cost, resources, and schedules in planning a chip design project
- Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements
- Model functionality and behavior, validate designs, and verify formal equivalency
- Apply EDA tools for logic synthesis, placement, and routing
- Analyze timing, noise, power, and electrical issues
- Prepare for manufacturing release and bring-up, from mastering ECOs to qualification
This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.
Sample Content
Online Sample Chapter
VSLI Design Implementation: Placement
Sample Pages
Download the sample pages (includes Chapter 8)
Table of Contents
- Chapter 1 Introduction
- Chapter 2 VLSI Design Methodology
- Chapter 3 Hierarchical Design Decomposition
- Chapter 4 Cell and IP Modeling
- Chapter 5 Characteristics of Functional Validation
- Chapter 6 Characteristics of Formal Equivalency Verification
- Chapter 7 Logic Synthesis
- Chapter 8 Placement
- Chapter 9 Routing
- Chapter 10 Layout Parasitic Extraction and Electrical Modeling
- Chapter 11 Timing Analysis
- Chapter 12 Noise Analysis
- Chapter 13 Power Analysis
- Chapter 14 Power Rail Voltage Drop Analysis
- Chapter 15 Electromigration (EM) Reliability Analysis
- Chapter 16 Miscellaneous Electrical Analysis Requirements
- Chapter 17 ECOs
- Chapter 18 Physical Design Verification
- Chapter 19 Design for Testability Analysis
- Chapter 20 Preparation for Tapeout
- Chapter 21 Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification