VHDL Design Representation and Synthesis, 2nd Edition

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Features

• A complete unified explanation of the VHDL language—Presented in one, self-contained section, before the discussion of synthesis.

  • Serves as a convenient, user-friendly reference. Ex.___

• Numerous examples of the modeling process—Illustrates the modeling process with numerous examples at varying levels of abstraction, and presents modeling styles for simulation efficiency and for compatibility with synthesis tools.

  • Makes the subject matter more tangible for students and easier to understand. Ex.___

• Structured design techniques for various forms of combinational and sequential logic.

  • Maps out these techniques in detail for students to more easily comprehend the process. Ex.___

• An explanation of the ASIC design process and the implementation technologies used in this process—e.g., PLDs, FPGAs, Gate Arrays, and Standard Cells.

• Synthesis with leading industrial tools—e.g., how synopsys synthesis tools are used for Standard Cell design; Xilinx tools for FPGAs. Provides performance comparisons between Standard Cell designs and FPGAs.

  • Gives a “blueprint” for students in how these tools are used and how they differ from each other. Ex.___

• Thorough description of the integration of VHDL into the design flow—Begins with executable specifications at the algorithmic level and concludes with the implementations at the gate or cell level suitable for use in custom or programmable integrated circuit chips.

  • Takes students through the entire process, enabling them to understand the significance of each aspect. Ex.___

• Introductory material on structured design concepts and design tools.

• Homework problems for each chapter—These are closely tied to the chapter material and reflect realistic design situations.

  • Provides students with tangible applications of the material under study, allowing them to put what they are learning into practice. Ex.___

• More than 300 references.

  • Offers students additional material to supplement the subject matter. Ex.___

Description

VHDL Design Representation and Synthesis, Second Edition is an exceptionally clear, thorough, and up-to-date introduction to today's leading approach to hardware design: synthesis using a hardware description language and today's leading synthesis tools. Armstrong and Gray begin with an introduction to structured design, and a unified explanation of the VHDL language and its key constructs. Next, they introduce the modeling process step by step, using many examples at varying levels of abstraction, and demonstrate techniques designed to maximize both simulation efficiency and compatibility with synthesis tools.

• Design tools: editors, simulators, checkers, analyzers, optimizers, and synthesizers
• VHDL: major constructs, lexical description, source files, data types, data objects, statements, and advanced features
• Fundamental VHDL modeling techniques: propagation and time delay, concurrency, scheduling, combinational logic, sequential logic, and primitives
• Integrating VHDL into the design flow, from executable specifications at the algorithmic level through implementations at the gate or cell level
• Modling PLDs, gate arrays, FPGAs (using Xilinx tools) and standard cells (using Synopsys tools)

This edition contains extensive new coverage of multilevel modeling, design with standard parts and ASICs data and control unit design, modeling for synthesis, and more. Review problems are included in each chapter, and over 300 references are provided. If you intend to design with VHDL, this is the book to start with.

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Table of Contents

Preface.


1. Structured Design Concepts.

The Abstraction Hierarchy. Textual vs Pictorial Representations. Types of Behavioral Descriptions. Design Process. Structural Design Decomposition. The Digital Design Space.

CAD Tool Taxonomy. Schematic Editors. Simulators. The Simulation System. Simulation Aids. Applications of Simulation. Synthesis Tools.

Major Language Constructs.

VHDL Source File. Data Types. Data Objects. Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL 93. Summary.

Modeling Delay in VHDL. The VHDL Scheduling Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives.

General Algorithmic Model Development in the Behavioral Domain. Representation of System Interconnections. Algorithmic Modeling of Systems.

Transition from Algorithmic to Data Flow Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine.

Accurate Gate Level Modeling. Error Checking. Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate Level Models. Modeling Races and Hazards. Approaches to Delay Control.

Design of Combinational Logic Circuits. Design of Sequential Logic Circuits. Design of Microprogrammed Control Units.

What is an ASIC? ASIC Circuit Technology. Types of ASICs. The ASIC Design Process. FPGA Synthesis.

Behavioral Model Development. The Semantics of Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits. Shared Resources. Flattening and Structuring. Effect of Modeling Style On Circuit Complexity.

Top-Down Design Methodology. Sobel Edge Detection Algorithm. System Requirements Level. System Definition Level. Architecture Design. Detailed Design at the RTL Level. Detailed Design at the Gate Level.

Benefits of Algorithmic Synthesis. Algorithmic Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art in High-Level Synthesis. Automated Synthesis of VHDL Constructs.

Preface

Preface

The purpose of this book is to integrate hardware description languages into the digital design process at all levels of abstraction. There are two main steps in this process: (1) development of a hardware description language model and (2) synthesis of the model into an ASIC logic circuit or FPGAs. In teaching this process, we use VHDL, the VHSIC Hardware Description Language. VHDL, whose development began in 1983 under DOD sponsorship, was further developed by the IEEE and released as IEEE Standard 1076 in 1987. Further improvements were incorporated since then and the language was re-released as an updated standard in 1993. Since that time, VHDL has evolved into a de facto industry standard for hardware description languages. In the opinion of the authors, it has the most comprehensive set of modeling constructs available in any hardware description language. For these reasons, VHDL was chosen as the base language for this book. We explore the language in an in-depth, unified manner.

Most books currently on the market that treat hardware description languages, particularly VHDL, are either: (1) language texts that cover the VHDL language thoroughly, but do not show how to integrate the language into the digital design process, or (2) logic design books that primarily use VHDL models as simulation tools to validate designs that are produced in the classical manner. This book fully integrates VHDL into the design process starting with a high-level executable model that provides an unambiguous, executable version of the specification, and concluding with a gate-level implementation.

In this book, synthesis is viewed as a multistep process, beginning with an English description which is transformed first into VHDL and then from VHDL into a circuit schematic. We discuss synthesis from two viewpoints: 1) the mappings: emphasis is placed on understanding the relationship between VHDL language constructs and the implied logic circuit. A full chapter is devoted to correct modeling style for synthesis; 2) the tools: we illustrate the synthesis process using two very popular tool sets, the Synopsys Design Analyzer and Compiler (for ASICs) and the Xilinx Foundation Series (for FPGAs). Since ASICs and FPGAs are the targets, a chapter is devoted to these technologies. The book also contains a chapter illustrating the complete top-design design process from specification to logic synthesis.

This book is written for three main educational purposes: (1) for a second course in logic design for undergraduate students in Electrical Engineering, Computer Engineering, and Computer Science; (2) for a graduate course dealing with hardware description languages and other design aids; and (3) for practicing engineers who wish to learn about design with hardware description languages. Thus the assumed background for the book is (1) a basic course in computer organization and logic design and (2) some knowledge of high-level languages, such as C, C++, or JAVA.

The authors use the text in a course, which is the second course in a logic design sequence. The students are either juniors in Computer Engineering, for whom the course is required, or Electrical Engineering seniors, for whom the course is an elective. In this semester length course we cover Chapters 1, 2, 3, 4, 5, 9, 10, and 11. The emphasis is on developing VHDL models in a conservative algorithmic style that can be synthesized. To support this in the laboratory, we use a PC version of ViewLogic, Inc.'s Workview for VHDL modeling and simulation and schematic capture. Xilinx software and XS40/XTEND boards are used for FPGA synthesis. We also em-ploy System View from Elanix to provide for high-level design of digital filters. Workstation-based Synopsys tools are used for ASIC synthesis. All students in our department have their own PCs, so the use of a PC-based system such as Workview has been effective in being able to serve the large number of students we normally teach in our second digital design course. For this same reason, we use telnet and dc_shell scripts for Synopsys synthesis. Typical assignments include:

1. An introductory assignment to familiarize students with Workview's VHDL modeling, simulation and schematic capture environment.
2. An assignment to develop and simulate a single VHDL behavioral model.
3. An assignment to develop a model of a counter, or some similar circuit. VHDL behavioral models are developed for counter flip-flops and gates, and the schematic capture capability of Workview is used to construct the structural model of the counter.
4. An assignment to translate a system description is first translated into a VHDL behavioral model which is simulated. This is typically a state machine such as an interface protocol, a vending machine, or a traffic light controller.
5. An introductory tutorial to the Xilinx Foundation Series Software.
6. An assignment to implement a small circuit in both Synopsys ASIC logic and FPGAs and compare speed of execution.
7. A fairly complicated FPGA project such as a booth multiplier, calculator, small processor, digital filter, or graphics display. For the filter, the codec on the XSTEND board is used for A/D and D/A comversion. The Xilinx filter code is developed using System View. The graphics display displays a pattern stored in RAM on a VGA monitor.

If used for a graduate course, the entire book can be covered in one semester. In such a course, one can cover the broad range of constructs in the language and examine in detail the language semantics for both simulation and synthesis. In our graduate course at Virginia Tech, we synthesize with Synopsys and validate synthesized models. We study ways to control the synthesis to achieve optimum circuits in a delay or area sense. High-level modeling tools such as Express VHDL, SPW, and System View are also covered. A comparison is done between VHDL and Verilog.

For this course, the student's laboratory assignments include:

1. An assignment to develop and simulate a single VHDL behavioral model.
2. An assignment to develop a model of a counter or some similar circuit. VHDL behavioral models are developed for counter flip-flops and gates, and then a VHDL structural model is developed for the whole system.
3. An assignment involving complex data types, e.g., using array aggregates and record types to implement a tabular representation of a finite state machine.
4. A system modeling assignment that involves the use of bus resolution and bus protocols. This system employs the IEEE 9 valued logic system. Examples include the URISC processor system in Chapter 6 or a histogram construction system for image processing.
5. An assignment where a model is written, simulated, and synthesized using both VHDL and Verilog and comparison's made
6. A semester project where the students model a system of their choice. One can choose projects, which stretch the language, i.e., involve applications that are not typical, such as modeling parallel processing systems or modeling systems which are not digital.

The book contains hundreds of VHDL models and code fragments. All code has been analyzed, and simulated, and synthesized (where required), using the Synopsys VHDL system. The only exception to this is the VHDL 93 code. In addition, the text contains over 300 homework problems with a wide range of difficulty. Types of problems include short answer questions, simple design problems, complex system design problems involving design, modeling, and simulation, and problems that require a study of a design or design tool issue. Some problems in this latter category would make good thesis projects!

Accompanying the book is a CD-ROM. On the CD are: 1) source files for all VHDL code in the book, 2) a set of projects accompanied by supporting data command files, and 3) packages to support common design paradigms. Problem and project solutions and Power Point lecture slides are available to instructors who adopt our text for classroom use.

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