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About
Features
- Free MIPS architecture simulator—Enables easy observation of the memory-mapped I/O, interrupts and exception processing, and delayed loads and delayed branches for a pipelined implementation.
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Allows students to learn how to write the fundamental assembly language code to implement the classical I/O algorithms; enables students to gain experience writing assembly language interrupt response routines, at the heart of any operating system.
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- Extensive pedagogy—Includes 67 programming exercises.
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Enables students to practice what they have learned.
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- Well-written and clearly organized.
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Provides students with the most up-to-date and easily understandable material.
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- Comprehensive Appendix A—Provides a quick source for all fundamental information needed to develop programs.
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Gives students a handy quick-reference for all fundamental programming information; can serve as a handbook in the future.
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Description
- Copyright 2004
- Dimensions: 7" x 9-1/4"
- Pages: 168
- Edition: 1st
- Book
- ISBN-10: 0-13-142044-5
- ISBN-13: 978-0-13-142044-1
For freshman/sophomore-level courses in Assembly Language Programming, Introduction to Computer Organization, and Introduction to Computer Architecture.
Students using this text will gain an understanding of how the functional components of modern computers are put together and how a computer works at the machine language level. MIPS architecture embodies the fundamental design principles of all contemporary RISC architectures. By incorporating this text into their courses, instructors will be able to prepare their undergraduate students to go on to upper-division computer organization courses.
Sample Content
Table of Contents
1. The MIPS Architecture.
2. Algorithm Development in Pseudocode.
3. Number Systems.
4. PCSpim: The MIPS Simulator.
5. Efficient Algorithm Development.
6. Function Calls Using the Stack.
7. Reentrant Functions.
8. Memory Mapped I/O.
9. Exceptions and Interrupts.
10. A Pipelined Implementation.
11. Floating-Point Instructions.
Appendix A: Quick Reference.
Appendix B: ASCII Codes.
Appendix C: Integer Instruction Set.
Appendix D: Macro Instructions.
Appendix E: A Modified Trap Handler.
Appendix F: Floating-Point Instruction Set.
Index.