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Application-Specific Integrated Circuits
- By Michael Smith
- Published Jun 10, 1997 by Addison-Wesley Professional.
Book
- Sorry, this book is no longer in print.
About
Features
VLSI-systems design. ASIC design, using commercial tools and pre-designed cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC-design methods have become increasingly popular in industry for a wide range of applications.
The book covers both semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design - design entry, logic synthesis, simulation, and test - and then to physical design - partitioning, floorplanning, placement, and routing. You will find here, in practical well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and to complete your own design.
Features
- Broad coverage includes, in one information-packed volume, cell-based ICs, gate arrays, field-programmable gate arrays (FPGAs), and complex programmable logic devices (PLDs).
- Examples throughout the book have been checked with a wide range of commercial tools to ensure their accuracy and utility.
- Separate chapters and appendixes on both Verilog and VHDL, including material from IEEE standards, serve as a complete reference for high-level, ASIC-design entry.
Description
- Copyright 1997
- Edition: 1st
- Book
- ISBN-10: 0-201-50022-1
- ISBN-13: 978-0-201-50022-6
This comprehensive book on application-specific integrated circuits (ASICs) describes the latest methods in VLSI-systems design. ASIC design, using commercial tools and pre-designed cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC-design methods have become increasingly popular in industry for a wide range of applications.
The book covers both semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design - design entry, logic synthesis, simulation, and test - and then to physical design - partitioning, floorplanning, placement, and routing. You will find here, in practical well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and to complete your own design.
Features
- Broad coverage includes, in one information-packed volume, cell-based ICs, gate arrays, field-programmable gate arrays (FPGAs), and complex programmable logic devices (PLDs).
- Examples throughout the book have been checked with a wide range of commercial tools to ensure their accuracy and utility.
- Separate chapters and appendixes on both Verilog and VHDL, including material from IEEE standards, serve as a complete reference for high-level, ASIC-design entry.
0201500221B04062001
Sample Content
Table of Contents
(Each chapter concludes with a Summary, Problems, Bibliography and References.)
1. Introduction to ASICs.
Types of ASIC.
Full-Custom ASICs.
Standard-Cell?Based ASICs.
Gate-Array?Based ASICs.
Channeled Gate-Array.
Channelless Gate-Array.
Structured Gate-Array.
Programmable Logic Devices.
Field-Programmable Gate Arrays.
Design Flow.
Case Study.
Economics of ASICs.
Comparison Between ASIC Technologies.
Product Cost.
ASIC Fixed Costs.
ASIC Variable Costs.
ASIC Cell Libraries.
2. CMOS Logic.
CMOS Transistors.
P-Channel Transistors.
Velocity Saturation.
SPICE Models.
Logic Levels.
The CMOS Process.
Sheet Resistance.
CMOS Design Rules.
Combinational Logic Cells.
Pushing Bubbles.
Drive Strength.
Transmission Gates.
Exclusive-OR Cell.
Sequential Logic Cells.
Latch.
Flip-Flop.
Clocked Inverter.
Datapath Logic Cells.
Datapath Elements.
Adders.
A Simple Example.
Multipliers.
Other Arithmetic Systems.
Other Datapath Operators.
I/O Cells.
Cell Compilers.
3. ASIC Library Design.
Transistors as Resistors.
Transistor Parasitic Capacitance.
Junction Capacitance.
Overlap Capacitance.
Gate Capacitance.
Input Slew Rate.
Logical Effort.
Predicting Delay.
Logical Area and Logical Efficiency.
Logical Paths.
Multistage Cells.
Optimum Delay.
Optimum Number of Stages.
Library-Cell Design.
Library Architecture.
Gate-Array Design.
Standard-Cell Design.
Datapath-Cell Design.
4. Programmable ASICs.
The Antifuse.
Metal?Metal Antifuse.
Static RAM.
EPROM and EEPROM Technology.
Practical Issues.
FPGAs in Use.
Specifications.
PREP Benchmarks.
FPGA Economics.
FPGA Pricing.
Pricing Examples.
5. Programmable ASIC Logic Cells.
Actel.
ACT 1 Logic Module.
Shannonés Expansion Theorem.
Multiplexer Logic as Function Generators.
ACT 2 and ACT 3 Logic Modules.
Timing Model and Critical Path.
Speed Grading.
Worst-Case Timing.
Actel Logic Module Analysis.
Xilinx LCA.
XC3000 CLB.
XC4000 Logic Block.
XC5200 Logic Block.
Xilinx CLB Analysis.
Altera FLEX.
Altera MAX.
Logic Expanders.
Timing Model.
Power Dissipation in Complex PLDs.
6. Programmable ASIC I/O Cells.
DC Output.
Totem-Pole Output.
Clamp Diodes.
AC Output.
Supply Bounce.
Transmission Lines.
DC Input.
Noise Margins.
Mixed-Voltage Systems.
AC Input.
Metastability.
Clock Input.
Registered Inputs.
Power Input.
Power Dissipation.
Power-On Reset.
Xilinx I/O Block.
Boundary Scan.
Other I/O Cells.
7. Programmable ASIC Interconnect.
Actel ACT.
Routing Resources.
Elmoreés Constant.
RC Delay in Antifuse Connections.
Antifuse Parasitic Capacitance.
ACT 2 and ACT 3 Interconnect.
Xilinx LCA.
Xilinx EPLD.
Altera MAX 5k and 7k.
Altera MAX 9k.
Altera FLEX.
8. Programmable ASIC Design Software.
Design Systems.
Xilinx.
Actel.
Altera.
Logic Synthesis.
FPGA Synthesis.
The Halfgate ASIC.
Xilinx.
Actel.
Altera.
Comparison.
FPGA Vendors.
Third-party Software.
9. Low-Level Design Entry.
Schematic Entry.
Hierarchical Design.
The Cell Library.
Names.
Schematic Icons and Symbols.
Nets.
Schematic Entry for ASICs and PCBs.
Connections.
Vectored Instances and Buses.
Edit-in-Place.
Attributes.
Netlist Screener.
Schematic-Entry Tools.
Back-Annotation.
Low-level Design Languages.
ABEL.
CUPL.
PALASM.
PLA Tools.
EDIF.
EDIF Syntax.
An EDIF Netlist Example.
An EDIF Schematic Icon.
An EDIF Example.
CFI Design Representation.
CFI Connectivity Model.
10. VHDL.
A Counter.
A 4-bit Multiplier.
An 8-bit Adder.
A Register-Accumulator.
Zero-Detector.
A Shift-Register.
A State Machine.
A Multiplier.
Packages and Test Bench.
Syntax and Semantics of VHDL.
Identifiers and Literals.
Entity and Architecture.
Packages and Libraries.
Standard Package.
Std_logic_1164 Package.
Textio Package.
Other Packages.
Creating Packages.
Interface Declaration.
Port Declaration.
Generics.
Type Declaration.
Other Declarations.
Object Declarations.
Subprogram Declarations.
Alias and Attribute Declarations.
Predefined Attributes.
Sequential Statements.
Wait Statement.
Assertion and Report Statements.
Assignment Statements.
Procedure Call.
If Statement.
Case Statement.
Other Sequential Control Statements.
Operators.
Arithmetic.
IEEE Synthesis Packages.
Concurrent Statements.
Block Statement.
Process Statement.
Concurrent Procedure Call.
Concurrent Signal Assignment.
Concurrent Assertion Statement.
Component Instantiation.
Generate Statement.
Execution.
Configurations and Specifications.
An Engine Controller.
11. Verilog HDL.
A Counter.
Basics of the Verilog Language.
Verilog Logic Values.
Verilog Data Types.
Other Wire Types.
Numbers.
Negative Numbers.
Strings.
Operators.
Arithmetic.
Hierarchy.
Procedures and Assignments.
Continuous Assignment Statement.
Sequential Block.
Procedural Assignments.
Timing Controls and Delay.
Timing Control.
Data Slip.
Wait Statement.
Blocking and Non-blocking Assignments.
Procedural Continuous Assignment.
Tasks and Functions.
Control Statements.
Case and If Statement.
Loop Statement.
Disable.
Fork and Join.
Logic Gate Modeling.
Built-in Logic Models.
User-defined Primitives.
Modeling Delay.
Net and Gate Delay.
Pin-to-pin Delay.
Altering Parameters.
A Viterbi Decoder.
Viterbi Encoder.
The Received Signal.
Testing the System.
Verilog Decoder Model.
Other Verilog Features.
Display Tasks.
File I/O Tasks.
Timescale, Simulation, and Timing Check Tasks.
PLA Tasks.
Stochastic Analysis Tasks.
Simulation Time Functions.
Conversion Functions.
Probability Distribution Functions.
Programming Language Interface.
The Viterbi Decoder.
12. Logic Synthesis.
A Logic-Synthesis Example.
A Comparator/MUX.
An Actel Version of the Comparator/MUX.
Inside a Logic Synthesizer.
Synthesis of the Viterbi Decoder.
ASIC I/O.
Flip-Flops.
The Top-Level Model.
Verilog and Logic Synthesis.
Verilog Modeling.
Delays in Verilog.
Blocking and Nonblocking Assignments.
Combinational Logic in Verilog.
Multiplexers In Verilog.
The Verilog Case Statement.
Decoders In Verilog.
Priority Encoder in Verilog.
Arithmetic in Verilog.
Sequential Logic in Verilog.
Component Instantiation in Verilog.
Datapath Synthesis in Verilog.
VHDL and Logic Synthesis.
Initialization and Reset.
Combinational Logic Synthesis in VHDL.
Multiplexers in VHDL.
Decoders in VHDL.
Adders in VHDL.
Sequential Logic in VHDL.
Instantiation in VHDL.
Shift Registers and Clocking in VHDL.
Adders and Arithmetic Functions.
Adder-subtracter and Donét Cares.
Finite-State Machine Synthesis.
FSM Synthesis in Verilog.
FSM Synthesis in VHDL.
Memory Synthesis.
Memory Synthesis in Verilog.
Memory Synthesis in VHDL.
The Multiplier.
Messages During Synthesis.
The Engine Controller.
Performance-Driven Synthesis.
Optimization of the Viterbi Decoder.
13. Simulation.
The Different Types of Simulation.
The Comparator/MUX Example.
Structural Simulation.
Static Timing Analysis.
Gate-Level Simulation.
Net Capacitance.
Logic Systems.
Signal Resolution.
Logic Strength.
How Logic Simulation Works.
VHDL Simulation Cycle.
Delay.
Cell Models.
Primitive Models.
Synopsys Models.
Verilog Models.
VHDL Models.
VITAL Models.
SDF in Simulation.
Delay Models.
Using a Library Data Book.
Input-Slope Delay Model.
Limitations of Logic Simulation.
Static Timing Analysis.
Hold Time.
Entry Delay.
Exit Delay.
External Setup Time.
Formal Verification.
An Example.
Understanding Formal Verification.
Adding an Assertion.
Completing a Proof.
Switch-Level Simulation.
Transistor-Level Simulation.
A PSpice Example.
SPICE Models.
14. Test.
The Importance of Test.
Boundary-Scan Test.
BST Cells.
BST Registers.
Instruction Decoder.
TAP Controller.
Boundary-Scan Controller.
A Simple Boundary-Scan Example.
BSDL.
Faults.
Reliability.
Fault Models.
Physical Faults.
Stuck-at Fault Model.
Logical Faults.
IDDQ Test.
Fault Collapsing.
Fault Collapsing Example.
Fault Simulation.
Serial Fault Simulation.
Parallel Fault Simulation.
Concurrent Fault Simulation.
Nondeterministic Fault Simulation.
Fault-Simulation Results.
Fault-Simulator Logic Systems.
Hardware Acceleration.
A Fault Simulation Example.
Fault Simulation in an ASIC Design Flow.
Automatic Test-Pattern Generation.
The D-Calculus.
A Basic ATPG Algorithm.
The PODEM Algorithm.
Controllability and Observability.
Scan Test.
Built-in Self-test.
LFSR.
Signature Analysis.
A Simple BIST Example.
Aliasing.
LFSR Theory.
LFSR Example.
MISR.
A Simple Test Example.
Test Logic Insertion.
How the Test Software Works.
ATVG and Fault Simulation.
Test Vectors.
Production Tester Vector Formats.
Test Flow.
The Viterbi Decoder Example.
15. ASIC Construction.
Physical Design.
CAD Tools.
Methods and Algorithms.
System Partitioning.
Estimating ASIC Size.
Power Dissipation.
Switching Current.
Short-Circuit Current.
Subthreshold and Leakage Current.
FPGA Partitioning.
ATM Simulator.
Automatic Partitioning with FPGAs.
Partitioning Methods.
Measuring Connectivity.
A Simple Partitioning Example.
Constructive Partitioning.
Iterative Partitioning Improvement.
The Kernighan?Lin Algorithm.
The Ratio-Cut Algorithm.
The Look-ahead Algorithm.
Simulated Annealing.
Other Partitioning Objectives.
16. Floorplanning and Placement.
Floorplanning.
Floorplanning Goals and Objectives.
Measurement of Delay in Floorplanning.
Floorplanning Tools.
Channel Definition.
I/O and Power Planning.
Clock Planning.
Placement.
Placement Terms and Definitions.
Placement Goals And Objectives.
Measurement of Placement Goals and Objectives.
Placement Algorithms.
Eigenvalue Placement Example.
Iterative Placement Improvement.
Placement Using Simulated Annealing.
Timing-Driven Placement Methods.
A Simple Placement Example.
Physical Design Flow.
Information Formats.
SDF for Floorplanning and Placement.
PDEF.
LEF and DEF.
17. Routing.
Global Routing.
Goals and Objectives.
Measurement of Interconnect Delay.
Global Routing Methods.
Global Routing Between Blocks.
Global Routing Inside Flexible Blocks.
Timing-Driven Methods.
Back-annotation.
Detailed Routing.
Goals and Objectives.
Measurement of Channel Density.
Algorithms.
Left-Edge Algorithm.
Constraints and Routing Graphs.
Area-Routing Algorithms.
Multilevel Routing.
Timing-Driven Detailed Routing.
Final Routing Steps.
Special Routing.
Clock Routing.
Power Routing.
Circuit Extraction and DRC.
SPF, RSPF and DSPF.
Design Checks.
Mask Preparation.
Appendix A. VHDL Resources.
BNF.
VHDL Syntax.
BNF Index.
Bibliography.
References.
Appendix B. Verilog HDLResources.
Explanation of the Verilog HDL BNF.
Verilog HDL Syntax.
BNF Index.
Verilog HDL LRM.
Bibliography.
References.
Glossary of Symbols and Acronyms.
Index. 0201500221T04062001
Preface
In 1988 I began to teach full-custom VLSI design. In 1990 I started teaching ASIC design instead, because my students found it easier to get jobs in this field. I wrote a proposal to The National Science Foundation (NSF) to use electronic distribution of teaching material. Dick Lyon helped me with preparing the first few CD-ROMs at Apple, but Chuck Seitz, Lynn Conway, and others explained to me that I was facing a problem that Carver Mead and Lynn had experienced in trying to get the concept of multichip wafers adopted. It was not until the publication of the Mead-Conway text that people accepted this new idea. It was suggested that I must generate interest using a conventional format before people would use my material in a new one (CD-ROM or the Internet). In 1992 I stopped writing papers and began writing this book-a result of my experiments in computer-based education. I have nearly finished this book twice. The first time was a copy of my notes. The second time was just before the second edition of Weste and Eshragian was published-a hard act to follow. In order to finish in 1997 I had to stop updating and including new ideas and material and now this book consists of three parts: Chapters 1-8 are an introduction to ASICs, 9-14 cover ASIC logical design, and 15-17 cover the physical design of ASICs.
The book is intended for a wide audience. It may be used in an undergraduate or graduate course. It is also intended for those in industry who are involved with ASICs. Another function of this book is an "ASIC Encyclopedia," and therefore I have kept the background material needed to a minimum. The book makes extensive use of industrial tools and examples. The examples in Chapters 2 and 3 use tools and libraries from MicroSim (PSpice), Meta Software (HSPICE), Compass Design Automation (standard-cell and gate-array libraries), and Tanner Research (L-Edit). The programmable ASIC design examples in Chapter 4-8 use tools from Compass, Synopsys, Actel, Altera, and Xilinx. The examples in Chapter 9 (covering low-level design entry) used tools from Exemplar, MINC, AMD, UC Berkeley, Compass, Capilano, Mentor Graphics Corporation, and Cadence Design Automation. The VHDL examples in Chapter 10 were checked using QuickVHDL from Mentor, V-System Plus from Model Technology, and Scout from Compass. The Verilog examples in Chapter 11 were checked using Verilog-XL from Cadence, V-System Plus, and VeriWell from Wellspring Solutions. The logic synthesis examples in Chapter 12 were checked with the ASIC Synthesizer product family from Compass and tools from Mentor, Synopsys, and UC Berkeley. The simulation examples in Chapter 13 were checked with QuickVHDL, V-System/Plus, PSpice, Verilog-XL, DesignWorks from Capilano Computing, CompassSim, QSim, MixSim, and HSPICE. The test examples in Chapter 14 were checked using test software from Compass, Cadence, Mentor, Synopsys and Capilano's DesignWorks. The physical design examples in Chapters 15-17 were generated and tested using Preview, Gate Ensemble, and Cell Ensemble (Cadence) as well as ChipPlanner, ChipCompiler, and PathFinder (Compass). All these tools are installed at the University of Hawaii.
I wrote the text using FrameMaker. This allows me to project the text and figures using an LCD screen and an overhead projector. I used a succession of Apple Macintosh computers: a PowerBook 145, a 520, and lastly a 3400 with 144 MB of RAM, which made it possible for me to create updates to the index in just under one minute. Equations are "live" in FrameMaker. Thus, can be updated in a lecture and the new result displayed. The circuit layouts are color EPS files with enhanced B&W PICT previews created using L-Edit from Tanner Research. All of the Verilog and VHDL code examples, compiler and simulation input/output, and the layout CIF that were used in the final version are included as conditional (hidden) text in the FrameMaker document, which is approximately 200 MB and just over 6,000 pages (my original source material spans fourteen 560 MB optical disks). Software can operate on the hidden text, allowing, for example, a choice of simulators to run the HDL code live in class. I converted draft versions of the VHDL and Verilog LRMs and related standards to FrameMaker and built hypertext links to my text, but copyright problems will have to be solved before this type of material may be published. I drew all the figures using FreeHand. They are "layered" allowing complex drawings to be built-up slowly or animated by turning layers on or off. This is difficult to utilize in book form, but can be done live in the classroom.
A course based on FPGAs can use Chapter 1 and Chapters 4-8. A course using commercial semicustom ASIC design tools may use Chapters 1-2 or Chapters 1-3 and then skip to Chapter 9 if you use schematic entry, Chapter 10 (if you use VHDL), or Chapter 11 (if you use Verilog) together with Chapter 12. All classes can use Chapters 13 and 14. FPGA-based classes may skim Chapters 15-17, but classes in semicustom design should cover these chapters. The chapter dependencies-Y (X) means Chapter Y depends on X-are approximately: 1, 2(1), 3(2), 4(2), 5(4), 6(5), 7(6), 8(7), 9(2), 10(2), 11(2), 12(10 or 11), 13(2), 14(13), 15(2), 16(15), 17(16).
I used the following references to help me with the orthography of complex terms, style, and punctuation while writing: Merriam-Webster's Collegiate Dictionary, 10th edition, 1996, Springfield, MA: Merriam-Webster, ISBN 0-87779-709-9, PE1628.M36; The Chicago Manual of Style, 14th edition, Chicago: University of Chicago Press, 1993, ISBN 0-226-10389-7, Z253.U69; and Merriam-Webster's Standard American Style Manual, 1985, Springfield, MA: Merriam-Webster, ISBN 0-87779-133-3, PN147.W36. A particularly helpful book on technical writing is BUGS in Writing by Lyn DuprE, 1995, Reading, MA: Addison-Wesley, ISBN 0-201-60019-6, PE1408.D85 (this book grew from Lyn DuprE's unpublished work, Style SomeX, which I used).
The bibliography at the end of each chapter provides alternative sources if you cannot find what you are looking for. I have included the International Standard Book Number (ISBN) and Library of Congress (LOC) Call Number for books, and the International Standard Serial Number (ISSN) for journals (see the LOC information system, LOCIS, at http://www.loc.gov). I did not include references to material that I could not find myself (except where I have noted in the case of new or as yet unpublished books). The electronic references given in this text have (a last) access date of 4/19/97 and omit enclosing <> if the reference does not include spaces.
I receive a tremendous level of support and cooperation from industry in my work. I thank the following for help with this project: Cynthia Benn and Lyn DuprE for editing; Helen Goldstein, Peter Gordon, Susan London-Payne, Tracy Russ, and Juliet Silveri, all at Addison-Wesley; Matt Bowditch and Kim Arney at Argosy; Richard Lyon, Don North, William Rivard, Glen Stone, the managers of the Newton group, and many others at Apple Computer who provided financial support; Apple for providing support in the form of software and computers; Bill Becker, Fern Forcier, Donna Isidro, Mike Kliment, Paul McLellan, Tom Schaefer, Al Stein, Rich Talburt, Bill Walker, and others at Compass Design Automation and VLSI Technology for providing the opportunity for me to work on this book over many years and allowing me to test material inside these companies and on lecture tours they sponsored; Chuck Seitz at Caltech; Joseph Cavallaro, Bernie Chern, Jerry Dillion, Mike Foster, and Paul Hulina at the NSF; the NSF for financial support with a Presidential Young Investigator Award; Jim Rowson and Doug Fairbairn; Constantine Anagnostopolous, Pin Tschang and members of the ASIC design groups at Kodak for financial support; the disk-drive design group at Digital Equipment Corp. (Massachusetts), Hewlett-Packard, and Sun Microsystems for financial support; Ms. MOSIS and all of the staff at MOSIS who each have helped me at one point or another by providing silicon, technical support, and documentation; Bob Brodersen, Roger Howe, Randy Katz, and Ed Lee of UC Berkeley for help while I was visiting UCB; James Plummer of Stanford, for providing me with access to the Terman Engineering Library as a visiting scholar, as well as Abbas El Gamal and Paul Losleben, also at Stanford, for help on several occasions; Don Bouldin at University of Tennessee; Krzysztof Kozminski at MCNC for providing Uncle layout software; Gershom Kedem at Duke University for the public domain tools his group has written; Sue Drouin, JosE De Castro, and others at Mentor Graphics Corporation in Oregon for providing documentation and tools; Vahan Kasardjhan, Gail Grego, Michele Warthen, Steve Gardner, and others at the University Program at Cadence Design Automation in San Jose who helped with tools, documentation, and support; Karen Dorrington and the Cadence group in Massachusetts; Andy Haines, Tom Koppin, Sherri Mieth, Velma Miller, Robert Nalesnik, Mike Sarpa, Telle Whitney, and others at Actel for software, hardware, parts, and documentation; Peter Alfke, Leslie Baxter, Brad Fawcett, Chris Kingsley, Karlton Lau, Rick Mitchell, Scott Nance, and Richard Ravel at Xilinx for support, parts, software, and documentation; Greg Hedmann at NorComp for data on FPGAs; Anna Acevedo, Suzanne Bailey, Antje MacNaughton, Richard Terrell, and Altera for providing software, hardware programmers, parts, and documentation; the documentation group and executive management at LSI Logic for tools, libraries, and documentation; Toshiba, NEC, AT&T/NCR, Lucent, and Hitachi (for documentation); NEC for their visiting scholar program at UH; Fred Furtek, Oscar Naval, and Claire Pinkham at Concurrent Logic, Randy Fish at Crosspoint, and Gary Banta at Plus Logic-all for documentation; Paul Titchener and others at Comdisco (now part of Cadence Design Automation) for providing design tools; John Tanner and his staff at Tanner Research for providing their tools and documentation; Mahendra Jain and Nanci Magoun, who let me debug early prototypes at the IDEA conference organized by ASIC Technology and News; Exemplar for providing documentation on its tools; MINC for providing a copy of its FPGA software and documentation; Claudia Traver and Synopsys for tools and documentation; Mentor Graphics Corporation for providing its complete range of software; Alain Hanover and others at ViewLogic for providing tools; Mary Shepherd and Jerry Walker at IEEE for help with permissions; Meta Software for providing HSPICE; Chris Dewhurst and colleagues at Capilano Computing for its design tools; Greg Seltzer (Model Technology) and Charley Rowley for providing V-System Plus with online documentation prototypes; Farallon and Telebit for the software and hardware I used for early experiments with telelectures. Many research students at the University of Hawaii helped me throughout this project including: Chin Huang, Clem Portmann, Christeen Gray, Karlton Lau, Jon Otaguro, Moe Lwin, Troy Stockstad, Ron Jorgenson, Derwin Mattos, William Rivard, Wendy Ching, Anil Aggrawal, Sudhakar Jilla, Linda Xu, Angshuman Saha, Harish Pareek, Claude van Ham, Wen Huang, Kumar Vadhri, Yan Zhong, Yatin Acharya, and Barana Ranaweera. Each of the classes that used early versions of this text at the University of Hawaii at Manoa have also contributed by finding errors. The remaining errors are mine.
Palo Alto and Honolulu, 1997
0201500221P04062001