VSLI Design Implementation: Placement
- 8.1 Global Floorplanning of Hierarchical Units
- 8.2 Parasitic Interconnect Estimation
- 8.3 Cell Placement
- 8.4 Clock Tree Local Buffer Placement
- 8.5 Summary
- Further Research
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This chapter is from the book
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This chapter is from the book
8.1 Global Floorplanning of Hierarchical Units
Prior to detailed placement of cells in block netlists (and the global cells at the top of the SoC hierarchy), a physical floorplan of the chip design is required. As briefly described in Section 3.1, the floorplan typically represents the first level of the SoC model hierarchy; it is uncommon to further develop a “floorplan within a floorplan” for the physical design of subsequent levels of the SoC hierarchy. The glue logic functionality at the top hierarchical level is commonly allocated to channels between block floorplan boundaries. An alternative methodology would be to define abutting block floorplan regions and insert global glue logic within various blocks. The advantage of the reduced channel area is offset by the additional dependency of global cell and route data on block-level physical verification and electrical analysis.
The physical floorplan data include the global power and ground grids and global clock distribution, typically originating from a PLL hard IP macro that serves as the clock reference source. The power and ground grids in the channels require specific design consideration, as the glue logic circuits include high-drive-strength cells with high switching activity (e.g., signal repowering buffers, state-repeating register banks).
The floorplan may include allocated routing track segments for major signal busses between blocks in the overall SoC architecture, including global repeaters. These preroutes assist with the definition of the block-level floorplan pins, area, and aspect ratio.
The development of floorplan pins is a critical facet of SoC design planning. The pin definition for each block’s primary inputs and primary outputs includes the following:
The pin width, corresponding to the interconnect wire width to use with the global signal
The pin metal layer for the interface between global and block routing
The pin multipatterning decomposition assignment
For advanced process nodes, depending on the metal layer, the pin definition may also need to include a multipatterning assignment that is consistent with the “color” associated with the pin’s routing track. Alternative methods for pin location assignment include the following:
Internal pin locations—The pin may not be assigned to the block perimeter; rather, it might be given internal coordinates. The goal of using internal pin locations would be to improve timing. As mentioned in Section 7.2, the accuracy of block-level timing closure is improved if the cells connected to block PIs/POs are placed in close proximity to the pin. An internal pin location may allow optimal placement of block netlist cells with connectivity to both global and internal signals. A high density of internal pins may have an adverse impact on global routing, however, to accommodate both over-the-block global routes and pin accessibility.
A flexible range of locations—A pin may be allocated to a range of locations (e.g., a segment of a specific floorplan edge) but not assigned fixed coordinates. In this case, the block placement flow includes pin location assignment as part of cell assignment; rather than using fixed pin locations to influence cell placement, the algorithm is able to include pin placement as an optimization objective. The methodology decision to use flexible pin locations as input to the block cell placement flow introduces an interdependency between global route planning and block physical implementation.
Floorplan areas allocated to hierarchical design blocks are typically rectangular, although EDA vendor tools for physical design may support rectilinear definitions. The aspect ratio of each floorplan block is a key factor in subsequent routing and path timing closure. A high aspect ratio block has a skewed ratio of available horizontal to vertical wiring tracks, and thus it may have difficulty subsequently closing on routing.
The SoC floorplan includes blocks associated with the chip input/output pad circuits, usually located on the die perimeter. Mixed-signal IP cores are also typically associated with unique floorplan blocks, such as PLLs, data conversion functions (ADCs, DACs), and high-speed interface SerDes IP. These blocks also require unique power/ground distribution design. The I/O circuits are likely to use additional voltages different from internal cells (e.g., VDDIO, VDD_1_2, VDD_1_5). Mixed-signal cores require separate low-noise supply rails (e.g., VDDA, GNDA) that are electrically distinct from the rails for digital switching networks.
Power-gating design is reflected within each block, as represented by the power format file description (described in Section 7.6). The internal power and ground distribution to enable deep sleep behavior is not extended globally, as depicted in Figure 8.1.
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Figure 8.1 The block internal power (or ground) distribution to support power gating is not extended globally.