- Low-Power Design: An Overview
- Low-Voltage, Low-Power Design Limitations
- Silicon-On-Insulator (SOI)
- From Devices to Circuits
- References
This chapter is from the book
This chapter is from the book
This chapter is from the book
1.3 Silicon-On-Insulator (SOI)
SOI is one of the leading technologies that offer high packing density as well as high-speed and low-power operations. SOI has a distinct characteristic—the delay improvement in the circuit depends very much on the circuit topology and its design [32]. Generally, the more complex the circuit is, the more impact SOI provides. This understanding is especially applicable to circuits using stacked transistors since the body voltage is rarely negative with respect to the source. The performance improvement of SOI over bulk varies according to the type of circuit as well, namely static, dynamic, or array. SOI also has an impact on the path delay. Since the improvement of individual circuits in SOI depends on their topologies, the improvement in overall cycle time is the net effect of the improvement of all the individual circuits composing the frequency-limiting critical paths.
The advantages rendered by SOI do not come by without circuit design challenges. These concerns are mainly caused by the uncertainty in the potential of the FET body. The potential of the body with respect to ground is a function of many factors, including the circuit topology and switching history. This "history effect" makes the delay through a particular circuit difficult to predict without full knowledge of the prior states and transitions of the circuit. This effect on delays varies according to the circuit topology, environment, and other factors. Another point of concern is the parasitic bipolar current, which puts dynamic circuits and some static circuit families at risk. Even though it is not a serious problem in fully restoring circuits, it becomes alarming when it comes to topologies, which combine a large number of parallel devices, such as wide muxes and OR gates. The floating body in SOI transistors also leads to uncertainty in threshold voltages, which in turn means lower noise margins for dynamic circuits. A low noise figure requires changes in dynamic circuit design and redesigning circuits that were originally intended for a bulk technology. Several design techniques are commonly used to improve the noise figure without adversely affecting the circuit delay. These include cross-connecting inputs to stacked devices, predischarging intermediate nodes, and remapping logic. Device self-heating can be problematic with SOI. This phenomenon is attributed to the thermal resistance of the buried oxide layer. Vulnerable devices are those in a high current state for a significant portion of the clock cycle, such as some off-chip drivers.