- 1.1 Digital Electronic System
- 1.2 I/O Signaling Standards
- 1.3 Power and Signal Distribution Network
- 1.4 Signal and Power Integrity
- 1.5 Power Noise to Signal Coupling
- 1.6 Concurrent Design Methodology
- References
This chapter is from the book
This chapter is from the book
This chapter is from the book
1.3 Power and Signal Distribution Network
Chapter 4, "System Interconnects," describes the power and signal distribution networks, and their interactions. For a semiconductor I/O interface, the driver and receiver circuits are implemented in the chip. The chip is packaged and then placed on a PCB. The block diagram of the PDN and signal network is shown in Figure 1.5.
)
Figure 1.5 Power and signal distribution network
PCB PDN comprises Voltage Regulator Module (VRM), power/ground plane structure, and decoupling capacitors. The VRM converts the input voltage from the power supply to the desired DC output. PCB typically has a multilayer stackup, and power and ground planes form a cavity structure. Package PDN can have a power/ground plane structure and package capacitors. The package connects to the chip at the pad or the bump. The power routes from the bump to the I/O circuit through the on-chip interconnects.
The signal network is routed on the chip, on the package, and then on the PCB. The impedance mismatch at the interface can cause the signal reflections. The two basic types of transmission lines in a package and PCB are microstrip and stripline. Differential signaling utilizes coupled lines. Chapter 4 also describes the details of the on-chip power and signal networks, and Chapter 9, "Measurement Techniques," illustrates the characterization of on-chip components.