- Chapter 3: Microprocessor Types and Specifications
- Pre-PC Microprocessor History
- Processor Specifications
- SMM (Power Management)
- Superscalar Execution
- MMX Technology
- SSE (Streaming SIMD Extensions)
- 3DNow and Enhanced 3DNow
- Dynamic Execution
- Dual Independent Bus (DIB) Architecture
- Processor Manufacturing
- PGA Chip Packagingx
- Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
- Processor Sockets and Slots
- Zero Insertion Force (ZIF) Sockets
- Processor Slots
- CPU Operating Voltages
- Heat and Cooling Problems
- Math Coprocessors (Floating-Point Units)
- Processor Bugs
- Processor Update Feature
- Processor Codenames
- Intel-Compatible Processors (AMD and Cyrix)
- P1 (086) First-Generation Processors
- P2 (286) Second-Generation Processors
- P3 (386) Third-Generation Processors
- P4 (486) Fourth-Generation Processors
- P5 (586) Fifth-Generation Processors
- Pseudo Fifth-Generation Processors
- Intel P6 (686) Sixth-Generation Processors
- Other Sixth-Generation Processors
- Itanium (P7/Merced) Seventh-Generation Processors
- Processor Upgrades
- Processor Troubleshooting Techniques
Processor Codenames
Intel, AMD, and Cyrix have always used codenames when talking about future processors. The codenames are normally not supposed to become public, but often they do. They can often be found in magazine articles talking about future generation processors. Sometimes, they even appear in motherboard manuals because the manuals are written before the processors are officially introduced. Table 3.19 lists processor codenames for reference.
Table 3.19 Processors and Codenames
AMD Codename |
AMD Processor |
X5 |
5x86-133 [Socket 3] |
SSA5 |
K5 (PR75-100) [Socket 5, 7] |
5k86 |
K5 (PR120-200) [Socket 7] |
K6 |
Original K6 core; killed after AMD acquired NexGen |
NX686 |
NexGen core that became the K6 [Socket 7] |
Little Foot |
0.25μ K6 [Socket 7] |
Chompers |
K6-2 (formerly K6-3D) [Socket 7, Super 7] |
Sharptooth |
K6-3 (formerly K6 Plus-3D) [Super 7] |
Argon |
Original codename for K7 |
K7 |
Athlon [Slot A] |
K75 |
0.18μ Athlon [Slot A] |
Spitfire |
Duron [Socket A] |
Thunderbird |
Athlon [Slot A, Socket A] |
Mustang |
Athlon w/copper interconnects [Slot A, Socket A] |
Corvette |
Mobile Athlon [Socket A] |
SledgeHammer |
K8 (64-bit CPU) |
Cyrix Codename |
Cyrix Processor |
M6 |
486DX [Socket 1, 2, 3] |
M7 |
486DX2/DX4 [Socket 3] |
M9 |
5x86 [Socket 3] |
M1sc |
5x86 [Socket 3] |
Chili |
5x86 project |
M1 |
6x86 (3.3v or 3.52v version) [Socket 7] |
M1L |
6x86L (2.8v/3.3v split version) [Socket 7] |
M1R |
Switch from 3M SGS process to 5M IBM process for 6x86 |
M2 |
6x86MX/M-II [Socket 7, Super 7] |
Cayenne |
MXi and Gobi core |
Jedi |
Original codename for Joshua (before Gobi) |
Gobi |
Former codename for Joshua |
Joshua |
VIA/Cyrix-III [Socket 370] |
Jalapeno |
Former codename for Mojave |
Mojave |
Cyrix/VIA M3 [Socket 370] |
Serrano |
Cyrix/VIA M4 |
C5 |
Samuel core (Winchip-4 plus on-Die L2 cache) |
Samuel |
Cyrix/VIA chip based on Winchip-4 [Socket 370] |
Intel Codename |
Intel Processor |
P23 |
486SX [Socket 1, 2, 3] |
P23S |
486SX SL-enhanced [Socket 1, 2, 3] |
P23N |
487SX (coprocessor) [Socket 1] |
P4 |
486DX [Socket 1, 2, 3] |
P4S |
486DX SL-enhanced [Socket 1, 2, 3] |
P24 |
486DX2 [Socket 1, 2, 3] |
P24S |
486DX2 SL-enhanced [Socket 1, 2, 3] |
P24D |
486DX2 (write-back enhanced version) [Socket 3] |
P24C |
486DX4 [Socket 3] |
P23T |
486DXODP (486 overdrive) [Socket 1, 2, 3] |
P4T |
486DXODPR (486 overdrive) [Socket 1, 2, 3] |
P24T |
PODP5V (Pentium OverDrive for 486) [Socket 2, 3] |
P24CT |
Pentium OverDrive for 486DX4 (3.3v core) [Socket 2, 3] |
P5 |
Pentium (60/66MHz versions) [Socket 4] |
P5T |
Pentium OverDrive (120, 133) [Socket 4] |
P54C |
Pentium (75-120MHz versions) [Socket 5, 7] |
P54CQS |
Pentium (120-133MHz version) [Socket 5, 7] |
P54CS |
Pentium (120-200MHz versions) [Socket 7] |
P54CTA |
Pentium OverDrive (125, 150, 166) [Socket 5, 7] |
Intel Codename |
Intel Processor |
P55C |
Pentium MMX [Socket 7] |
P54CTB |
Pentium MMX OverDrive [Socket 5, 7] |
Tillamook |
mobile Pentium MMX |
P6 |
Pentium Pro [Socket 8] |
P6T |
Pentium II OverDrive [Socket 8] |
Klamath |
Pentium II [Slot 1] |
Drake |
Pentium II Xeon [Slot 2] |
Deschutes |
0.25μ Pentium II [Slot 1 & 2] |
Tonga |
Mobile Pentium II |
Covington |
Celeron (cacheless Deschutes) [Slot 1] |
Mendocino |
Celeron (128KB on-die L2) [Slot 1, Socket 370] |
Dixon |
Mobile Pentium II (256KB on-die L2) |
Katmai |
Pentium III [Slot 1] |
Tanner |
Pentium III Xeon [Slot 2] |
Coppermine |
0.18μ PIII w/256KB on-die L2 [Slot 1, Socket 370] |
Cascades |
Coppermine Xeon (256KB on-die L2) [Slot 2] |
Coppermine-128 |
Celeron III (128KB on-die L2) [Socket 370] |
Timna |
Celeron III w/integral chipset hub |
P68 |
Former codename for Willamette |
Willamette |
Pentium IV [Socket 423] |
Foster |
Pentium IV server [Socket 603] |
Gallatin |
0.13μ successor to Foster [Socket 603] |
Northwood |
Mobile Pentium IV |
P7 |
Former codename for Merced |
Merced |
Itanium (IA64) [Slot M] |
McKinley |
2nd generation Itanium [Slot M] |
Madison |
0.13μ McKinley [Slot M] |
Deerfield |
Low-cost Madison [Slot M] |
Note that the codenames and information listed in these tables is not officially released, so by the time many of these future processors come out, names or specifications may change. Most companies who actually get this information from Intel are required to sign non-disclosure agreements which prevents them from sharing this information. This information has been gathered from a number of contacts and sources.