- Chapter 3: Microprocessor Types and Specifications
- Pre-PC Microprocessor History
- Processor Specifications
- SMM (Power Management)
- Superscalar Execution
- MMX Technology
- SSE (Streaming SIMD Extensions)
- 3DNow and Enhanced 3DNow
- Dynamic Execution
- Dual Independent Bus (DIB) Architecture
- Processor Manufacturing
- PGA Chip Packagingx
- Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
- Processor Sockets and Slots
- Zero Insertion Force (ZIF) Sockets
- Processor Slots
- CPU Operating Voltages
- Heat and Cooling Problems
- Math Coprocessors (Floating-Point Units)
- Processor Bugs
- Processor Update Feature
- Processor Codenames
- Intel-Compatible Processors (AMD and Cyrix)
- P1 (086) First-Generation Processors
- P2 (286) Second-Generation Processors
- P3 (386) Third-Generation Processors
- P4 (486) Fourth-Generation Processors
- P5 (586) Fifth-Generation Processors
- Pseudo Fifth-Generation Processors
- Intel P6 (686) Sixth-Generation Processors
- Other Sixth-Generation Processors
- Itanium (P7/Merced) Seventh-Generation Processors
- Processor Upgrades
- Processor Troubleshooting Techniques
Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
Abandoning the chip-in-a-socket approach used by virtually all processors until this point, the Pentium II/III chips are characterized by their Single Edge Contact (SEC) cartridge design. The processor, along with several L2 cache chips, is mounted on a small circuit board (much like an oversized memory SIMM), which is then sealed in a metal and plastic cartridge. The cartridge is then plugged into the motherboard through an edge connector called Slot 1, which looks very much like an adapter card slot.
By placing the processor and L2 cache as separate chips inside a cartridge, Intel now has a CPU module that is easier and less expensive to make than the Pentium Pro that preceded it. The Single Edge Contact (SEC) cartridge is an innovative—if a bit unwieldy—package design that incorporates the backside bus and L2 cache internally. Using the SEC design, the core and L2 cache are fully enclosed in a plastic and metal cartridge. These subcomponents are surface mounted directly to a substrate (or base) inside the cartridge to enable high-frequency operation. The SEC cartridge technology allows the use of widely available, high-performance industry standard Burst Static RAMs (BSRAMs) for the dedicated L2 cache. This greatly reduces the cost compared to the proprietary cache chips used inside the CPU package in the Pentium Pro.
A less expensive version of the SEC is called the Single Edge Processor (SEP) package. The SEP package is basically the same circuit board containing processor and (optional) cache as the Pentium II, but without the fancy plastic cover. The SEP package plugs directly into the same Slot 1 connector used by the standard Pentium II. Four holes on the board allow for the heat sink to be installed.
Slot 1 is the connection to the motherboard and has 242 pins. The Slot 1 dimensions are shown in Figure 3.6. The SEC cartridge or SEP processor is plugged into Slot 1 and secured with a processor-retention mechanism, which is a bracket that holds it in place. There may also be a retention mechanism or support for the processor heat sink. Figure 3.7 shows the parts of the cover that make up the SEC package. Note the large thermal plate used to aid in dissipating the heat from this processor. The SEP package is shown in Figure 3.8.
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Figure 3.6 Pentium II Processor Slot 1 dimensions (metric/English).
Figure 3.7 Pentium II Processor SEC package parts.
Figure 3.8 Celeron Processor SEP package front-side view.
With the Pentium III, Intel introduced a variation on the SEC packaging called SECC2 (Single Edge Contact Cartridge version 2). This new package covers only one side of the processor board and allows the heat sink to directly attach to the chip on the other side. This direct thermal interface allows for better cooling, and the overall lighter package is cheaper to manufacture. Note that a new Universal Retention System, consisting of a new design plastic upright stand, is required to hold the SECC2 package chip in place on the board. The Universal Retention System will also work with the older SEC package as used on most Pentium II processors, as well as the SEP package used on the slot based Celeron processors, making it the ideal retention mechanism for all Slot 1-based processors. Figure 3.9 shows the SECC2 package.
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Figure 3.9 SECC2 packaging used in newer Pentium II and III processors.
The main reason for going to the SEC and SEP packages in the first place was to be able to move the L2 cache memory off the motherboard and onto the processor in an economical and scalable way. Using the SEC/SEP design, Intel can easily offer Pentium II/III processors with more or less cache and faster or slower cache.