Introduction to a Signal Integrity Engineer's Companion

This chapter is from the book

Signal Integrity Engineer's Companion, A: Real-Time Test and Measurement and Design Simulation

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This chapter is from the book

This chapter is from the book 

Signal Integrity Engineer's Companion, A: Real-Time Test and Measurement and Design Simulation

Learn More Buy

1.4 The Need for Real-Time Test and Measurement

As data rates increase, it is ever more difficult to detect and debug noise and signal aberrations in a prototype or production model. A rigorous regime of signal integrity measurements can provide the means for the engineer to trace sources of noise or glitches and provide the wherewithal for him or her to eradicate the root causes of signal aberrations. Apart for the requirements of test and debug, there is often a need for a product to operate in a global market, and many designers are increasingly concerned with compliance measurements. Complying with industry standards ensures interoperability among system elements, where discrete system components from various manufacturers successfully interconnect and communicate. Compliance measurements usually entail a series of prescribed acquisition and analysis steps, which are carried out on a completed product. However, successful compliance design and testing often depend on eliminating signal integrity problems in the early phases of a design. Ideally the designer or test engineer locates signal integrity errors during the initial simulation of a product's development, as mentioned previously. However, a primary aim of the SI engineer must be to understand the role played by electronic bench instrumentation and portable test equipment in the pursuit of signal integrity. Today, the SI engineer needs to understand the latest methodologies that are used to achieve signal integrity. They are founded on the interrelationships between device simulation, circuit simulation, and real-time test and measurement. Apart from the fundamental theoretical concepts, or abstract mathematical models, the engineer must understand the practical issues that lie at the heart of signal integrity engineering. Remember that simulation is only a model, and a model is an imperfect replica of a real component or system. In many cases there is no substitute for a prototype and a real-time test phase, which at the very least will allow real-world data to be fed into the simulation.

One of the most demanding aspects of modern digital system design and debug is the successful measurement of the analog content of high-speed digital signals, where complex multilayer boards, the high density of interconnects, and highly integrated systems have made successful probing an exact science. Ideally the measurement system bandwidth, including that of the probe, should be at least three times the frequency of the signals to be observed. Above all, the edges of a digital signal must be considered when making a measurement. For instance, a standard 5 Gbps data rate serial bus signal requires at least a 15 GHz measurement bandwidth and a true differential probe that has a rise time of less than 35 picoseconds. Otherwise, the probe would at best fail to show any analog aberrations and at worse would simply stop the bus. Ultra-low loading and a diversity of attachment methods are needed to ensure fast, positive connection with minimal effect on signals.

Experienced engineers know that signal integrity is the result of constant vigilance during the design, simulation, and real-time test processes. It's all too easy for signal integrity problems to get compounded as a design evolves. An aberration that goes unnoticed in the early stages of a design can cause erratic behavior in a product, which can entail many hours of demanding test and debug to correct. An experienced engineer plans ahead and pays special attention to signal integrity issues in the early stages of a design. In particular, the engineer decides during the specification phase what signals need to be probed and how access is to be provided to signals of interest.

1.4.1 Timing Budgets and the Analog View

A signal integrity problem may first seem to be a misplaced digital pulse or timing error. However, the cause of the problem in a high-speed digital system can often be related to the analog characteristics of a digital signal. In many cases a digital problem can be fairly easy to pinpoint when an errant digital signal is successfully probed and the analog representation of the flawed digital signal is exposed. Analog characteristics can become digital faults when low-amplitude signals turn into incorrect logic states, or when slow rise times cause pulses to shift in time. An innovative test and measurement technique is to use a logic analyzer and oscilloscope in unison. The test technique is to show a digital pulse stream along with a simultaneous analog view of the same pulses, where both waveforms are shown on a single display, as shown in Figure 1-6. This technique is becoming a standard debug methodology, and the debug method is frequently the first step in tracking down an SI problem. Figure 1-6 is a real-time view of a digital data stream exhibiting a timing error. The analog view clearly shows the cause of the timing error as an amplitude aberration on the trailing edge of the digital pulse.

Figure 1-6 Digital pulse streams and a simultaneous analog view of the same pulses, where both waveforms are shown on a single display.

In any discussion of signal integrity, signal transitions deserve special attention. For example, the timing diagram shown in Figure 1-7 shows two digital inputs feeding an ordinary AND gate. The gray trace for Input A shows the correct pulse. Superimposed on it is an analog view, a distorted signal shown as a black trace, of the actual signal. Due to its slow rise time, the actual signal does not cross the required threshold value until much later than it should. Consequently, the output pulse from the AND gate is significantly narrower than it should be; the correct pulse width is shown in gray. The integrity of the signal on Input A is very poor, with serious consequences for the timing of digital elements elsewhere in the system. This type of SI problem typically causes timing errors in subsequent logic steps. Such dilemmas often require careful analysis for successful debugging.

Figure 1-7 The gray traces have the required signal characteristics, and the black traces are the actual analog signals; this simple example is an AND gate. Clearly Input A has a slow rise time and crosses the logic threshold too late, which results in an output timing error.

Suppose the output went on to become part of a memory address. The short pulse might cause the memory to see logic 0 where logic 1 should exist and therefore select a different memory location than the one that is expected. The content of that location, of course, is inappropriate for the transaction at hand. The end result is an invalid transaction, raising the all-too-familiar question of whether the bug is inherently a hardware or software failure.

Slow signal transition edges can lead to intermittent system faults even if they are not causing repeatable errors. Timing budgets in high-speed digital systems allow very little time for signal rise and fall transitions. Setup and hold times have scientifically decreased in recent years. Modern electronic memory systems are a typical example of setup and hold times in the low hundreds of picoseconds. Slowly changing edges can leave too little margin in the timing budget for data transactions to be valid and stable, as implied in Figure 1-8. The relationships shown in Figure 1-8 are exaggerated to emphasize the concept. These two simple examples show some of the potential unwanted effects resulting from too slow an edge transition. The majority of SI problems in high-speed digital systems commonly are related to the effects of fast switching edges and their associated high-frequency signal content.

Figure 1-8 Although not to scale and exaggerated, Clock A is seen to clock the data with a slow rise time, leaving the system with greater susceptibility to noise, with the possibility of double clocking and metastability. The faster Clock B edge results in improved reliability, and the timing budget is improved.

One of the major timing concerns in SI engineering is the setup and hold timing values that are specified for clocked digital devices. Setup and hold timing are at the heart of application-specific integrated circuit (ASIC) functional verification measurements. Setup time is defined as how long the data must be in a stable and valid state before the clock edge occurs. Hold time is how long that data state must remain stable and valid after the clock edge. In the high-speed digital devices used for computing and communications, both setup and hold timing values may be as low as a few hundred picoseconds.

Transients, edge aberrations, glitches, and other intermittencies can cause setup and hold violations. Figure 1-9 is a typical setup and hold timing diagram. In this example, the data envelope is narrower than the clock. This emphasizes the fact that with today's high-speed logic, transition times and setup and hold values can be very brief, even when the cyclical rate or signal frequency is relatively slow.

Figure 1-9 A typical setup and hold timing diagram.

There are three common approaches to evaluating a device's setup and hold performance. A number of other timing parameters can be verified using either a low-speed or high-speed functional test:

• Low-speed tests are a fairly coarse functional verification procedure, but they are often adequate. In some cases it is not necessary to take quantitative measurements of the actual setup and hold values that are specified on a device's data sheet. If a device can tolerate a broad clock placement range, the timing test may be as simple as running a low-speed functional data pattern, adjusting the position of the clock edge relative to the data, and observing the results on an oscilloscope. The oscilloscope trigger normally is set to a 50% level, which shows timing information before and after the clocking edge. A device tends to become metastable as it exceeds its setup and hold timing limitations, even at low speed. Metastability is an unpredictable state in which a device output may switch to either a logic 1 or logic 0 without any apparent regard for the logical input conditions. Similarly, excessive signal jitter may appear on the output when setup and hold tolerances are violated.
• High-speed tests typically require bursts of high-speed data, where the burst forms a functional test that exercises the device at rates approximating its intended operational frequency or higher. A signal source is used to deliver a block of data to the device under test (DUT) at data rates that are much higher than the basic low-speed functional test. However, this test process is still one of empirically finding a range of setup and hold values and specifying the system clock placement accordingly. Using a data generator with a repetitive data pattern, the recurring skew problems associated with high-speed setup and hold violations often can be isolated and rectified.
• Device self-test is an option on some contemporary source-synchronous and high-speed serial (HSS) components. The transmitter sends a known pattern to the receiver, which slides the location of the clock or strobe in time until data errors occur. The difference between the nominal clock or strobe location and the onset of data errors indicates how much margin exists in that interface.

1.4.2 Eye Diagrams

Eye diagrams have become one of the cornerstones of SI test and compliance measurements. The eye diagram is a regulatory measurement for validation and compliance testing of various industry-standard digitally transmitted signals. An eye diagram is a display that typically is viewed on an oscilloscope. It can efficiently reveal amplitude and timing errors in high-speed digital signals. The eye diagram shown in Figure 1-10 is built by overlaying digital signal waveform traces from successive logic signal cycle periods, or unit intervals. Waveform A in Figure 1-10 is a digital signal with exaggerated timing errors. Waveform B is the clock signal recovered from the signal shown as waveform A. Eye diagram A is generated by dividing waveform A into individual cycle periods and overlaying each cycle of waveform A. A number of measurements can be made on an eye diagram to quantify signal quality. One such measurement is the eye opening that relates to the signal timing, which is shown in Figure 1-10 as a gray area. Eye diagram B is produced from the recovered clock signal and shows the ideal eye opening, which indicates improved signal timing. Eye diagrams display serial data with respect to a clock that normally is recovered from the data signal using either hardware or software tools. In the eye diagram shown in Figure 1-11, the clock is recovered by a hardware-based reference or "golden" phase locked loop (PLL). The diagram displays all possible transition edges, both positive-going and negative-going, and both data states in a single window. The result is an image that somewhat resembles an eye, as shown in Figure 1-11.

Figure 1-10 Eye diagram formation.

Figure 1-11 An oscilloscope display showing a hardware-generated eye diagram. The gray areas are the mask violation zones.

In an ideal world, each new trace would line up perfectly on top of those that came before it. Also, the eye diagram would be composed of narrow lines representing the superimposed logic 1s and logic 0s. In the real world, signal integrity factors such as noise and jitter cause the composite trace to blur as it accumulates the logic 1s and logic 0s. The gray regions in Figure 1-11 have special significance; they are the violation zones used as mask boundaries during compliance testing. A compliance mask typically is produced by the instrument manufacturer in association with a standards body. In this case the gray polygon in the center defines the area in which the eye is widest. This encompasses the range of safe decision points for extracting the data content, the binary state, from a logic signal. The upper and lower gray bars define the signal's amplitude limits. If a signal peak penetrates the upper bar, for instance, it is considered a "mask hit" that will cause the compliance test to fail, although some standards may tolerate a small number of mask hits. More commonly, noise, distortion, transients, or jitter cause the trace lines to thicken. The eye opening shrinks, touching the inner gray polygon. This too is a compliance failure, because it reveals an intrusion into the area reserved for evaluating the logic state of the data bit. The compelling advantage of an eye diagram is that it enables a quick visual assessment of signal quality.

1.4.2.1 Simulated Eye Diagrams

Although the ideal eye diagram measurement is carried out in real time, it is sometimes impossible to extract. For example, a programmable logic device receiver equalization circuit typically is embedded within the device. However, it is possible to simulate the results using SPICE modeling. The upper part of Figure 1-12 shows a simulated eye diagram into the programmable logic device receiver after traversing a 40-inch backplane, without pre-emphasis. The lower part of Figure 1-12 shows the same signal after it has passed through receiver equalization.

Figure 1-12 SPICE simulated eye diagrams.

The eye diagrams shown in Figure 1-12 are a clear example of how an equalization circuit significantly improves the quality of a received signal, allowing reliable detection of logic states. Another example, Figure 1-13, shows the effects of too much pre-emphasis. You must select the optimum settings for both pre-emphasis and equalization. Overcompensation can cause additional issues within the system. It adds extra jitter, which closes the eye, making it impossible for the receiver to interpret the information. Figure 1-13 clearly shows the effect of adding too much pre-emphasis and equalization.

Figure 1-13 An eye diagram showing the exaggerated effects of too much pre-emphasis.

1.4.2.2 Real-Time Eye Diagrams

Real-time eye diagram debug methodologies often provide a shortcut that lets you quickly detect and correct SI problems. For example, some modern high-performance logic analyzers are combined with an oscilloscope and host troubleshooting tools that bring analog eye diagram analysis to the logic analyzer screen. The eye diagram is a real-time visualization tool that typically allows the designer to observe the data valid window, and general signal integrity, on clocked buses. This test methodology is a required compliance testing tool for many of today's buses, particularly the high-speed serial buses, but any signal line can be viewed as an eye diagram. Moreover, the logic analyzer eye diagram analysis can show wide parallel bus performance. It integrates hundreds of eye diagrams into one view that encompasses the leading and trailing edges of both positive-going and negative-going pulses that compose the bus signals. Figure 1-14 is an eye diagram where the contents of twelve address bus signals are superimposed. The benefit of observing bus lines simultaneously with an eye diagram is that it presents all possible logic transitions in a single view and allows fast assessment of the bus.

Figure 1-14 An eye diagram that simultaneously shows twelve bus signals.

An eye diagram can reveal analog problems in high-speed digital signals, such as slow rise times, transients, and incorrect logic levels. Figure 1-14 shows the performance of 12 parallel bus lines. The error encroaching into the mask is caused by an incorrect rise time in one of the bus signals.

The eye diagram shown in Figure 1-14 reveals an anomaly in the signals, which typically is shown in a distinctive color; the color indicates a relatively infrequent transition. In this example at least one of the signals has an edge that is outside the normal range. The mask feature built into the instrument helps locate the specific signal causing the problem. By drawing the mask in a particular way, such that the offending edge penetrates the mask area, the relevant signal can be isolated, highlighted, and brought to the front layer of the image. The result is shown in Figure 1-15, in which the flawed signal has been brought to the front of the display and highlighted in white. In this example the instrument identifies the aberrant edge and indicates a problem on the A3 (0) address bus signal. The origin of this particular problem is actually crosstalk, where the edge change is being induced by signals on an adjacent PCB trace.

Figure 1-15 The flawed signal has been brought to the front of the display.

The real-time functional verification and troubleshooting phase of the design in this example has described how a common SI problem is detected and resolved. The logic analyzer is often the first line of defense when testing digital functionality. However, digital problems can stem from analog signal issues, including edge degradation due to improper termination or crosstalk, as demonstrated here. By teaming the logic analyzer with an oscilloscope and evaluating time-correlated digital and analog signals on the same screen, you can see problems affecting either domain using an eye diagram. Today, low-cost mixed signal instruments with real-time eye diagram capabilities are used to test and debug high-performance digital systems. Specialist oscilloscopes are used for the more demanding tasks of compliance and interoperability tests.