This chapter is from the book
This chapter is from the book
This chapter is from the book
Microprocessor Clock Speeds
In the Pentium processor, two speed settings are established for the microprocessor—one speed for its internal core operations and a second speed for its external bus transfers. These two operational speeds are tied together through an internal clock multiplier system. The Socket 7 specification enabled system boards to be configured for different types of microprocessors using different operating speeds. In older systems, the operating speed of the microprocessor was configured through external settings.
Prior to Pentium II, all Pentium processors used 50, 60, or 66MHz external clock frequencies to generate their internal operating frequencies. The value of the internal multiplier was controlled by external hardware DIP-switch or jumper settings on the system board.
Pentium II processors moved to a 100MHz external clock and front-side bus. The Pentium III and all slot processors up to 1GHz continued to use the 100MHz clock and FSB. However, beginning with the Pentium III, the external clock speed was increased to 133MHz. At the same time, the Celeron processors retained the 66MHz clock and bus speeds up to 800MHz.
The Pentium 4 processors use external clocks of 100MHz and 133MHz. From these clock inputs, the Pentium 4's internal clock multipliers generate a core frequency of up to 3.06GHz and front-side bus frequencies of 400MHz, 533MHz, and 800MHz. They have also used four different special memory buses with different memory types. In Pentium 4 systems, it is possible to set clock speeds for the memory and front-side buses independently. The different memory bus configurations are designed to work with different types of advanced RAM and run at speeds of 400, 533, and 800MHz.
Newer processors, such as Intel's 3.46GHz Pentium 4 Extreme Edition, Pentium D dual core, and the Core 2 Duo, possess a 1066MHz FSB capability that works with 266MHz quad-pumped (that is, multiplied by 4) DDR2 RAM.
As mentioned previously in the chapter, double pumping a bus (also referred to as a dual-pumped, double-transition, or double data rate bus) involves transferring data on both the rising and falling edges of the clock signal's square wave. Similarly, quad pumping a bus (also referred to as a quad data rate or a double data rate 2 bus) transfers data four times during a clock cycle. This technique actually requires two versions of the clock signal that are 90 degrees out of phase. These techniques are used to transfer data between the microprocessor and RAM on the FSB using a lower, more stable clock frequency.
You may encounter some confusion because much of the industry uses the MHz terminology given in the previous paragraph to describe the FSB, when the proper terminology should be that the 266MHz actual bus clock frequency provides 1066MT/s across the bus (instead of 1066MHz).
In the example pointed out previously, the processor's advertised core speed is listed as 3.46GHz (3466MHz). That processor's documentation will show that an internal x13 multiplier is required to achieve this core operating speed. This means that the clock signal the noncore portions of the processor are using (which is also the system clock and the FSB clock) is running at 266MHz (3466/13). The quad-pumped bus-signaling technique used by these processors provides a transfer rate of 1066MT/s.
This discussion becomes even more complex when dealing with memory structures. In these discussions, you may also see the FSB bandwidth specified in terms of MBps. This value is arrived at by multiplying the bus's transfer rate by its width in bytes. Double- and quad-pumped memory operations are covered in detail in Chapter 4, "Random Access Memory (RAM)."