3.7 References
1. J. Bergeron. Writing Testbenches. Norwell, MA: Kluwer Academic Publishers, 2000.
2. www.cis.ohiostate.edu/~harrold/research
/regression_testing.htm
“Software Configuration Management with Elego ComPact.”
www.elego.de/compact/concept-automation.html, December 2000.“Scripts and Utilities.”
www.cs.utk.edu/~plank/plank/classes/cs494/notes“Creating and Using Makefiles.”
http://csc.uis.edu/resources/makefiles.html6. M. Keating and P. Bricaud. Reuse Methodology Manual for System-on-a-Chip Designs. Norwell, MA: Kluwer Academic Publishers, 1999.
7. F. Nekoogar. Timing Verification of Application Specific Circuits (ASICs). Upper Saddle River, NJ: Prentice Hall PTR, 1999.
8. P. Rashinkar, P. Paterson, and L. Singh. System-on-a-Chip Verification: Methodology and Techniques. Norwell, MA: Kluwer Academic Publishers, 2001.
9. H. Chang and L. Cooke. Surviving the SOC Revolution: A Guide to Platform-Based Designs. Norwell, MA: Kluwer Academic Publishers, July 1999.
10. Spring Tech Seminars, Verification 2001, Synopsys, Inc., Mountain View, CA.
11. S. Furber. ARM System-on-Chip Architecture, 2d edition. Reading, MA: Addison-Wesley, 2000.
“Processor SuperCore Approach to Designing Complex SOCs.”
Lucent Technologies, 2000 IP World Forum.“Multi-Platform, Mixed HDL, SOC Verification Environment.”
2000 System-on-a-Chip Design Conference, Westboro, MA.“Overcoming Challenges and Obstacles to System-on-a-Chip (SOC) Products.”
Marvell Semiconductor, Inc., Sunnyvale, CA..15. C. Settles (LSI Logic Corporation).
“Silicon Development Platform Simplifies System Design.”
2000 System-on-a-Chip Design Conference, Milpitas, CA.16. D. A. Burgoon, E. W. Powell, L. J. Sorensen, and J. A.S. Waitz (Hewlett-Packard Company).
“Next-Generation Concurrent Engineering for Complex Dual-Platform Subsystem Design.”
2000 System-on-a-Chip Design Conference, Santa Clara, CA.17. D. Tavana and S. K. Knapp (Triscend).