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Features

• NEW - Fully updated for the latest versions of Verilog HDL.

  • Helps students gain mastery over Verilog HDL's most important new features and capabilities.

• Broad coverage, from the fundamentals to the state-of-the-art—Logically progresses from basic techniques for building and simulating small Verilog models to advanced techniques for constructing tomorrow's most sophisticated digital designs.

  • Gives students a single source for all they need to know about Verilog HDL, from introductory-level techniques to the leading edge.

• Extensive examples, illustrations, and exercises—Illuminates every aspect of Verilog HDL design with practical examples and hands-on exercises.

  • Gives students maximum visual support and hands-on practice for mastering Verilog HDL rapidly, and retaining what they've learned.

• Learning objectives and summaries in every chapter—Includes many features designed to promote easier learning and deeper mastery.

  • Helps students prepare to learn new concepts, and then review what they have learned.

• CD-ROM—SILOS III simulation environment by Simucad, Inc.

  • Verilog simulator with a graphic users interface and the source code for examples in the book.

Description

Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.

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Downloads

As an aid to readers of Verilog HDL, 2nd Edition, we are making available the following downloads:

Files for UNIX Users

UNIX users may wish to download examples and solutions to selected exercises from book (60 kb, TGZ format). (Please note that this information is available for Windows users on the CD accompanying the book.)

CD Files

We are also making available for download the files from the CD accompanying the book (12.2 MB, ZIP format).

Sample Content

Downloadable Sample Chapter

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Table of Contents

(NOTE: Each chapter concludes with a Summary and Exercises.)

About the Author.


Foreword.


Preface.


Acknowledgments.

I. BASIC VERILOG TOPICS.

Evolution of Computer-Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts.

Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. 3. Basic Concepts.

Lexical Conventions. Data Types. System Tasks and Compiler Directives. 4. Modules and Ports.

Modules. Ports. Hierarchical Names. 5. Gate-Level Modeling.

Gate Types. Gate Delays. 6. Dataflow Modeling.

Continuous Assignments. Delays. Expressions, Operators, and Operands. Operator Types. Examples. 7. Behavioral Modeling.

Structured Procedures. Procedural Assignments. Timing Controls. Conditional Statements. Multiway Branching. Loops. Sequential and Parallel Blocks. Generate Blocks. Examples. 8. Tasks and Functions.

Difference between Tasks and Functions. Tasks. Functions. 9. Useful Modeling Techniques.

Procedural Continuous Assignments. Overriding Parameters. Conditional Compilation and Execution. Time Scales. Useful System Tasks.

II. ADVANCED VERILOG TOPICS.

Types of Delay Models. Path Delay Modeling. Timing Checks. Delay Back-Annotation. 11. Switch Level Modeling.

Switching-Modeling Elements. Examples. 12. User-Defined Primitives.

UDP basics. Combinational UDPs. Sequential UDPs. UDP Table Shorthand Symbols. Guidelines for UDP Design. 13. Programming Language Interface.

Uses of PLI. Linking and Invocation of PLI Tasks. Internal Data Representation. PLI Library Routines. 14. Logic Synthesis with Verilog HDL.

What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Synthesis Design Flow. Verification of the Gate-Level Netlist. Modeling Tips for Logic Synthesis. Example of Sequential Circuit Synthesis. 15. Advanced Verification Techniques.

Traditional Verification Flow. Assertion Checking. Formal Verification.

III. APPENDICES.

Strength Levels. Signal Contention. Advanced Net Types. Appendix B. List of PLI Routines.

Conventions. Access Routines. Utility (tf_) Routines. Appendix C. List of Keywords, System Tasks and Compiler Directives.

Keywords. System Tasks and Functions. Compiler Directives. Appendix D. Formal Syntax Definition.

Source Text. Declarations. Primitive Instances. Module and Generated Instantiation. UDP Declaration and Instantiation. Behavioral Statements. Specify Section. Expressions. General. Appendix E. Verilog Tidbits.
Appendix F. Verilog Examples.

Synthesizable FIFO Model. Behavioral DRAW Model. Bibliography.
Index.

Preface

Preface

During my earliest experience with Verilog HDL, I waslooking for a book that could give me a “jump start” on usingVerilog HDL. I wanted to learn basic digital design paradigms and the necessaryVerilog HDL constructs that would help me build small digital circuits, usingVerilog and run simulations. After I had gained some experience with buildingbasic Verilog models, I wanted to learn to use Verilog HDL to build largerdesigns. At that time, I was searching for a book that broadly discussed advancedVerilog-based digital design concepts and real digital design methodologies.Finally, when I had gained enough experience with digital design andverification of real IC chips, though manuals of Verilog-based products wereavailable, from time to time, I felt the need for a Verilog HDL book that wouldact as a handy reference. A desire to fill this need led to the publication ofthe first edition of this book.

It has been more than six years since the publication of thefirst edition. Many changes have occurred during these years. These years haveadded to the depth and richness of my design and verification experiencethrough the diverse variety of ASIC and microprocessor projects that I havesuccessfully completed in this duration. I have also seen state-of-the-artverification methodologies and tools evolve to a high level of maturity. TheIEEE 1364-2001 standard for Verilog HDL has been approved. The purpose of thissecond edition is to incorporate the IEEE 1364-2001 additions and introduce toVerilog users the latest advances in verification. I hope to make this editiona richer learning experience for the reader.

This book emphasizes breadth rather than depth. The bookimparts to the reader a working knowledge of a broad variety of Verilog-basedtopics, thus giving the reader a global understanding of Verilog HDL-baseddesign. The book leaves the in-depth coverage of each topic to the Verilog HDLlanguage reference manual and the reference manuals of the individualVerilog-based products.

This book should be classified not only as a Verilog HDLbook but, more generally, as a digital design book. It is important to realizethat Verilog HDL is only a tool used in digital design. It is the means to anend—the digital IC chip. Therefore, this book stresses the practicaldesign perspective more than the mere language aspects of Verilog HDL. WithHDL-based digital design having become a necessity, no digital designer canafford to ignore HDLs.  

Who Should Use This Book

The book is intended primarily for beginners andintermediate-level Verilog users. However, for advanced Verilog users, thebroad coverage of topics makes it an excellent reference book to be used inconjunction with the manuals and training materials of Verilog-based products.

The book presents a logical progression of Verilog HDL-basedtopics. It starts with the basics, such as HDL-based design methodologies, andthen gradually builds on the basics to eventually reach advanced topics, suchas PLI or logic synthesis. Thus, the book is useful to Verilog users withvarying levels of expertise as explained below.

• Students in logic design courses at universities

Part 1 of this book is ideal for a foundation semestercourse in Verilog HDL-based logic design. Students are exposed to hierarchicalmodeling concepts, basic Verilog constructs and modeling techniques, and thenecessary knowledge to write small models and run simulations.

• New Verilog users in the industry

Companies are moving to Verilog HDL-based design. Part 1 ofthis book is a perfect jump start for designers who want to orient their skillstoward HDL-based design.

• Users with basic Verilog knowledge who need to understand advanced concepts

Part 2 of this book discusses advanced concepts, such asUDPs, timing simulation, PLI, and logic synthesis, which are necessary forgraduation from small Verilog models to larger designs.

• Verilog experts

All Verilog topics are covered, from the basic modelingconstructs to advanced topics like PLIs, logic synthesis, and advanced verificationtechniques. For Verilog experts, this book is a handy reference to be usedalong with the IEEE Standard Verilog Hardware Description Language referencemanual.

The material in the book sometimes leans toward anApplication Specific Integrated Circuit (ASIC) design methodology. However, theconcepts explained in the book are general enough to be applicable to thedesign of FPGAs, PALs, buses, boards, and systems. The book uses Medium ScaleIntegration (MSI) logic examples to simplify discussion. The same conceptsapply to VLSI designs.

How This Book Is Organized

This book is organized into three parts.

Part 1, Basic Verilog Topics, covers all information that anew user needs to build small Verilog models and run simulations. Note that inPart 1, gate-level modeling is addressed before behavioral modeling. I havechosen to do so because I think that it is easier for a new user to see a 1-1correspondence between gate-level circuits and equivalent Verilog descriptions.Once gate-level modeling is understood, a new user can move to higher levels ofabstraction, such as data flow modeling and behavioral modeling, without losingsight of the fact that Verilog HDL is a language for digital design and is nota programming language. Thus, a new user starts off with the idea that Verilogis a language for digital design. New users who start with behavioral modelingoften tend to write Verilog the way they write their C programs. They sometimeslose sight of the fact that they are trying to represent hardware circuits byusing Verilog. Part 1 contains nine chapters.

Part 2, Advanced Verilog Topics, contains the advancedconcepts a Verilog user needs to know to graduate from small Verilog models tolarger designs. Advanced topics such as timing simulation, switch-levelmodeling, UDPs, PLI, logic synthesis, and advanced verification techniques arecovered. Part 2 contains six chapters.

Part 3, Appendices, contains information useful as areference. Useful information, such as strength-level modeling, list of PLIroutines, formal syntax definition, Verilog tidbits, and large Verilog examplesis included. Part 3 contains six appendices.

Index

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